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Condor's Cuzco RISC-V Core at Hot Chips 2025

(chipsandcheese.com)
154 points rbanffy | 1 comments | 30 Aug 25 14:18 UTC | HN request time: 0.5s | source
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daneel_w ◴[30 Aug 25 15:22 UTC] No.45075405[source]▶
"L2$, L3$, I$, D$". Well, OK.
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0x000xca0xfe ◴[30 Aug 25 15:43 UTC] No.45075590[source]▶
It's just shorthand for "level 2 cache", "level 3 cache", "instruction cache" and "data cache".
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daneel_w ◴[30 Aug 25 16:21 UTC] No.45075847[source]▶
Yes, obviously. It's just the first time I've seen a CPU designer/manufacturer use such relaxed "informality" in a spec sheet.
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1. jasonwatkinspdx ◴[31 Aug 25 02:51 UTC] No.45079925[source]▶
The slides are for Hot Chips, which is a very engineering focused venue. It's not your normal marketing stuff.