Condor's Cuzco RISC-V Core at Hot Chips 2025

It's just shorthand for "level 2 cache", "level 3 cache", "instruction cache" and "data cache".

Yes, obviously. It's just the first time I've seen a CPU designer/manufacturer use such relaxed "informality" in a spec sheet.

I've been seeing it more and more, especially with vendors that don't speak a western language on their spec sheets.

Everyone can tell what L1$ means, but what would L1 缓存 mean?

I follow RISC-V and see it all the time.

CPU manufacturers also aren't using Unicode, using the letter u instead of µ (micro), and the letter A instead of Å (the unit Ångström).

The slides are for Hot Chips, which is a very engineering focused venue. It's not your normal marketing stuff.