Condor's Cuzco RISC-V Core at Hot Chips 2025

"L2$, L3$, I$, D$". Well, OK.

Hmm?

It's just shorthand for "level 2 cache", "level 3 cache", "instruction cache" and "data cache".

Yes, obviously. It's just the first time I've seen a CPU designer/manufacturer use such relaxed "informality" in a spec sheet.

Ooh, I wonder what strings were put in those BASIC variables...

LET L2$="256 KiB"; LET L3$="8 MiB"

Cache is pronounced like cash, which the $ symbol is supposed to allude to.

Yes, they are obviously caches. I just didn’t understand your comment.

I've been seeing it more and more, especially with vendors that don't speak a western language on their spec sheets.

Everyone can tell what L1$ means, but what would L1 缓存 mean?

I follow RISC-V and see it all the time.

CPU manufacturers also aren't using Unicode, using the letter u instead of µ (micro), and the letter A instead of Å (the unit Ångström).

Wow, how have I never put 2 and 2 together on that.

You're not alone - it took me way longer than it should have done to figure that one out!

leading to the unfortunate abbreviation sometimes drawn on blackboards, "$hit"

It is an apt abbreviation if you visualize shit tightly packed in a container. And when you thrash the cache, shit hit the fan (and spills to VRAM.)

The slides are for Hot Chips, which is a very engineering focused venue. It's not your normal marketing stuff.