Ubuntu 25.10 Raises RISC-V Profile Requirements

Can you write a kernel patch / driver to trap the unsupported instructions and provide software implementations?

Rva20 lacks vector support and hypervisor instructions, among other things.

You’re welcome to put a ton of effort in for dogshit performance on a bunch or $35 SBCs but the rest of us will just upgrade

And don’t worry, some vendor won’t come in and magically save you - fedora is eyeing rv22 as their baseline.

That's the problem with open source, a bunch of people who once in their life want to "do it right" (right never comes). No adults in the room to say "this is what you got".

From a billion python packages in distribution package managers to broken screen sharing in Wayland, "right" isn't even what anyone wants.

The Linux Kernel has math coprocessor emulation (mainly floating point stuff) that can be enabled if your CPU doesn't include it. This was common with consumer CPUs in the 1990s and some embedded CPUs today.

Link here, although I'm sure it existed well before 2.6.12

https://www.kernelconfig.io/config_math_emulation

Can you rephrase your answer in a way that isn't brutally and unnecessarily hostile?

Honestly, it's because of the "can you do a ton of unpaid work to support my niche, non-commercial application" attitude of the OP, which I find to be extremely distasteful.

It's something I deal with frequently. I should not have taken it out on OP and I agree I could have communicated that much better.

Unfortunately, I can't edit my post or I would rephrase it significantly.

Sorry to user "Levitating", I was being a dick.

The profile includes not just additional instructions but also architectural requirements that can't be emulated. The size of cache lines and reservation sets must be 64 bytes (there is no instruction to query it, like there is on ARM). Data-independent execution latency is important for protecting cryptography against timing attacks.

Those were already in RVA22, and the difference from that to RVA23 could probably be emulated with traps though.

However, I think that some of the new instructions in RVA23 may potentially become very common in some binaries later on and could possibly trap so often that they would slow down those programs considerably.

> Honestly, it's because of the "can you do a ton of unpaid work to support my niche, non-commercial application" attitude of the OP, which I find to be extremely distasteful.

I understood their "Can you" as "Can one [theoretically]", more on the curiosity side than on the entitled side.

> The size of cache lines and reservation sets must be 64 bytes (there is no instruction to query it, like there is on ARM)

Thank goodness. What a colossal PITA trying to account for that across cluster switches.

Couldn't one completely disable cache thereby forcing a worst-case timing?