Optical PCIe 7.0 connection hits 128 GT/s

One bit, but it's a bit of the underlying signal layer which has a 1-2% redundancy over the actual data. PCIe 2.0 and earlier encode 8b data in 10b signal. 3.0 to 5.0 encode 128b data in 130b signal. 6.0 and 7.0 do a more complicated thing: https://pcisig.com/blog/pcie%C2%AE-60-specification-webinar-...

Also the speed is per lane, eg an x8 slot / port / device is called that because it has 8 lanes, which all transfer in parallel.

Edit: Nope, I misread. As reply notes, 16GB/s/lane.

So... That's about 16 terabytes per second per lane. AKA more bandwidth than I can imagine any use for, though I'm sure we will find ways to take advantage...

(Seriously, that's enough to move 16 largish laptop drives every second, on a single lane.)

>So... That's about 16 terabytes per second per lane.

If you assume 1T/s = 1b/s, 128GT/s is 128Gb/s = 16GB/s, not 16TB/s

Oops, yep, I misread that. Thanks for the correction

> it's a bit of the underlying signal layer which has a 1-2% redundancy over the actual data. PCIe 2.0 and earlier encode 8b data in 10b signal. 3.0 to 5.0 encode 128b data in 130b signal. 6.0 and 7.0 do a more complicated thing

Though the exact details of the overhead don't matter very much. They add 6% extra bits, good enough.

The part I want to call out as complicated/confusing is that a PCIe 7.0 lane puts out a voltage 64 billion times per second, but because each voltage is based on two bits that counts as 128 billion "transfers".

Assuming it was 16tb/s.... Imagine a JIT data lake loading stuff into main memory like brrr...

Actually at that point, a pcie7 nvme would be faster than ddr6

https://www.pcworld.com/article/2237799/ddr6-ram-what-you-sh...

That said, per-pin, 16GB/s seems to be the same ballpark as contemporary (to pcie7) main or graphics memory..... Like, actually more if I'm reading this right?

https://www.anandtech.com/show/21287/jedec-publishes-gddr7-s...

Yeah, the overhead isn't a big deal now that the overhead is single digit. Back when it was 20% in PCIe 2 it was a much bigger discrepancy.

Back then they were adding the overhead on top of the baseline speed, not subtracting it. With 1 and 2 you got the full 1/4 and 1/2 gbps of data per lane, but then 3 was only .985 instead of 1. So I'd argue that 6% for PCIe 6 and 7 is the most meaningful the overhead has ever been.

So, it's still bits all the way down? Whether we're talking about app, IP, or LL it's always bits/s, each level bringing a cost due to encapsulation. And then at PHY there's baud.

Is non-ISO unit "T" / "transfer" a marketing term or really specialised jargon? "transfer" just doesn't click in my mind, at best "a transfer" (countable) is about moving a sizeable aggregate chunk that has some semantic meaning, not a single fundamental quantum of information.

Unrelated: "gigatesla per second" is such a mind-boggling unit.

It's really specialized jargon that underscores the fact that it's raw bandwidth, not usable bandwidth.

Also, another common usage of transfers/second is with RAM. DDR5 6000MHz RAM is actually 6000MT/s, and the clock actually runs at 3000Hz ("DDR" == "double data rate").