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GlobalFoundries to Acquire MIPS

(mips.com)
224 points mshockwave | 7 comments | 08 Jul 25 16:57 UTC | HN request time: 0.868s | source | bottom
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alephnerd ◴[08 Jul 25 17:32 UTC] No.44502181[source]▶
Interesting but complementary foray into owning the end-to-end pipeline of chip design, fabrication, and packaging - especially for embedded use cases.

MIPS has also hitched it's horse to RISC-V now, and I am seeing a critical mass of talent and capital forming in that space.

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kragen ◴[08 Jul 25 17:43 UTC] No.44502288[source]▶
The critical mass of talent and capital forming in the RISC-V space happened in 02019 at Alibaba: https://www.cnx-software.com/2019/07/27/alibaba-unveils-xuan...

AFAIK MIPS still hasn't shipped a high-end processor competitive with the XuanTie 910 that article is about. And I think the billions of RISC-V microcontroller cores that have shipped already (10 billion as of 02022 according to https://wccftech.com/x86-arm-rival-risc-v-architecture-ships...) are also mostly not from MIPS.

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Findecanor ◴[08 Jul 25 21:00 UTC] No.44504041[source]▶
It was some time ago that MIPS did announce that they had competitive RISC-V cores and had signed customers for them: LG and in the automotive sector. I'd think those should be taped out by now, but who knows...

I think the C910 looks better on paper than it performs in practice. I hope that isn't the case for MIPS.

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kragen ◴[08 Jul 25 21:05 UTC] No.44504072[source]▶
Do you have any details?
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1. monocasa ◴[08 Jul 25 23:16 UTC] No.44504882[source]▶
Adding to what was said, it also suspiciously looks like a MIPS core with a RISC-V frontend strapped to it sort of like Qualcomm did with their Nuvia AArch64 core. Particularly stuff like the soft fill TLB from m-mode looks just like MIPS coprocessor 0.
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2. ajb ◴[08 Jul 25 23:30 UTC] No.44504956[source]▶
There's nothing especially wrong with using an existing backend design and transitioning it to another ISA; a number of teams did that from mips->arm and had success with the result. Of course, if you ship too early you may be missing some features.
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3. kragen ◴[08 Jul 25 23:43 UTC] No.44505019[source]▶
Yeah, my understanding was that shipping a high-performance MIPS core with RISC-V instruction decoding was precisely their plan. It sounded like a pretty good plan, really. But did they manage to actually ship one? Did you get a look at a datasheet?
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4. monocasa ◴[09 Jul 25 07:39 UTC] No.44507255[source]▶
No datasheet, but their commits to opensbi have been extremely enlightening wrt s and m modes.
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5. monocasa ◴[09 Jul 25 07:42 UTC] No.44507273[source]▶
> a number of teams did that from mips->arm and had success with the result.

Do you have any examples? Apple Silicon cores took pieces of the pwerficient cores, and everything else I know of either tweaked an official ARM design or started more or less from scratch.

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6. kragen ◴[09 Jul 25 07:48 UTC] No.44507311{3}[source]▶
Aha! I never would have thought to look there!
7. ajb ◴[09 Jul 25 14:22 UTC] No.44510412{3}[source]▶
Here is one: https://en.wikichip.org/wiki/cavium/microarchitectures/vulca...

I don't know the details of how much rework they had to do.

As I understand it cavium still sells processors but only directly to hyperscalers.

Ironically Cavium may have gone through the same process with their previous design, but given that they then acquired this one from broadcom, perhaps it didn't go very well! I have no concrete information though.