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Open Source and FPGA Maker Board for Networking

(privateisland.tech)
38 points private_island | 1 comments | 04 Jul 25 20:16 UTC | HN request time: 0.304s | source
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duskwuff ◴[05 Jul 25 05:13 UTC] No.44470231[source]▶
Maybe I'm just jaded and demanding, but:

1) As others mentioned, two GbE interfaces seems really limited for a 2025 project. Modern FPGAs can support 100GbE and up - I don't necessarily expect that on a hobbyist-level project, of course, but 1GbE is well behind the curve.

2) There don't appear to be any hardware design files (e.g. schematics, PCB layouts) in the Git repository. In fact, the only mention of the current FPGA is a single text file stating that "Cyclone 10 GX port in progress"...

3) There's basically zero open source support for Intel/Altera FPGAs. Yes, you can open-source your HDL, but the vendor tools are all closed-source and there's no alternatives.

replies(1): >>44472623 #
1. Aromasin ◴[05 Jul 25 13:19 UTC] No.44472623[source]▶
Agreed. They are using an Cyclone 10 GX - that's over $250 for a part from 2017...

If the restriction is wanting low price to suite the FPGAs open-source low-budget market, they'd be better off using a Lattice Certus-NX or something. 5Gbps SERDES on that for ~$40, or better yet a CertusPro-NX with 10Gbps SERDES for ~$70. Altera and Xilinx are just throwing away the sub-100K-LUT market to Lattice at this point, yet people are still building systems out using these expensive, antiquated parts. That's shelf pricing too - go through a distributor and it'd be 50% of that price!