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The 8-Bit Era's Weird Uncle: The TI-99/4A

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168 points rbanffy | 2 comments | | HN request time: 0s | source
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PaulHoule ◴[] No.43109081[source]
I guess next week they're going to get to the interesting bit which is how weird the architecture actually was on that thing...

https://en.wikipedia.org/wiki/TI-99/4A

Particularly it only had 256 bytes of RAM attached to the CPU but had (I think) 16 kb of RAM attached to the video controller which the CPU could read and write through I/O registers. You could use this for non-video storage but you couldn't access it directly.

Coding in BASIC could, at the very least, hide the insanity from you.

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phire ◴[] No.43109851[source]
It gets way weirder.

The TMS9900 didn't have any internal data registers. It only had a program counter, a status register, and a workspace pointer. Instead, it put the "registers" in that same 256 bytes of RAM. There were sixteen 16-bit registers which the workspace pointer pointed to.

The original idea was that this made for fast context switches, instead of dumping all registers to stack (it doesn't even have a stack pointer), just update the workspace pointer to point at a new set. But I have to assume this wasn't really used on the TI-99/4A, as there just wasn't enough RAM. Because your only other ram was locked behind the video controller, that 256 bytes had to contain all your registers, any your dynamically loaded code and any data you wanted rapid access to.

The TMS9900 is weird, because it's the only CPU of the early home computer era that wasn't designed for microcomputers. It's actually an implementation of the TI-990 mini-computer on a single chip and is actually used in later versions of the minicomputer. Those minicomputers had more than enough fast 16-bit memory to take advantage of this fast context switching.

Every other commonly used microprocessor of the 70s (8080, 6800, F8, 6502, RCA1802, Z80, 6809, 8086, 68000) was explicitly designed to target the low-cost microcomputer market.

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1. bregma ◴[] No.43117292[source]
If you disasembled the ROMs you'd find they're filled with BLWP/RTWP instructions. That's how subroutines were executed: Branch and Load Workspace Pointer. The BLWP instruction would load the WP and PC from the next two words and save the current WP/PC/SR into the new R13/14/15. RTWP would restore R13/14/15 into WP/PC/SR. The end result was a stack implemented as a linked list instead of a contiguous array. A lot of the subroutines in ROM just read/wrote tokens from/to the VRAM and then interpreted them as BASIC.
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2. OhMeadhbh ◴[] No.43117661[source]
Back when I lived in Texas and they started doing vanity plates, I applied for the plate "BLWP" (I lived in D/FW and visited Lubbock from time to time, so there was a non-zero chance someone driving by would get it.) After waiting a month, I got the letter from the DPS... no... someone beat me to it. So I guess there were at least two fans of the 990's memory-to-memory architecture out there.