YC is wrong about LLMs for chip design

I agree with most of the technical points of the article.

But there may still be value in YC calling for innovation in that space. The article is correctly showing that there is no easy win in applying LLMs to chip design. Either the market for a given application is too small, then LLMs can help but who cares, or the chip is too important, in which case you'd rather use the best engineers. Unlike software, we're not getting much of a long tail effect in chip design. Taping out a chip is just not something a hacker can do, and even playing with an FPGA has a high cost of entry compared to hacking on your PC.

But if there was an obvious path forward, YC wouldn't need to ask for an innovative approach.

There is an obvious path forward, but apparently this is a minority opinion, possibly fringe. It doesn't make the traditional tradeoffs.

A bit level (non von Neumann) general purpose systolic array could greatly speed up AI computations, along with almost everything else. It's a chip to do general purpose computation.

The chip design is almost trivial. I'd expect someone with a few years of experience could knock it out in a few days. I hope to field a design in the next TinyTapeout (I'm on a fixed income, so I've had to wait a while)

The real problem is programming. We're talking vast greenfields that go on forever. There's no good way to target the architecture, you certainly wouldn't want to use Verilog or any other HDL.