YC is wrong about LLMs for chip design

I agree with most of the technical points of the article.

But there may still be value in YC calling for innovation in that space. The article is correctly showing that there is no easy win in applying LLMs to chip design. Either the market for a given application is too small, then LLMs can help but who cares, or the chip is too important, in which case you'd rather use the best engineers. Unlike software, we're not getting much of a long tail effect in chip design. Taping out a chip is just not something a hacker can do, and even playing with an FPGA has a high cost of entry compared to hacking on your PC.

But if there was an obvious path forward, YC wouldn't need to ask for an innovative approach.

you could say it is the naive arrogance of the beginner mind.

seen here as well when george-hotz attempts to overthow the chip companies with his plan for an ai chip https://geohot.github.io/blog/jekyll/update/2021/06/13/a-bre... little realizing the complexity involved. to his credit, he quickly pivoted into a software and tiny-box maker.

> But if there was an obvious path forward, YC wouldn't need to ask for an innovative approach.

How many experts do YC have on chip design?

> But if there was an obvious path forward

Even obvious can be risky. First it's nice to share the risk, second more investments come with more connections.

As for LLMs boom. I think finally we'll realize that LLM with algorithms can do much more than just LLM. 'algorithms' is probably a bad word here, I mean assisting tools like databases, algorithms, other models. Then only access API can be trained into LLM instead of the whole dataset for example.

I know several founders who went through YC in the chip design space, so even if the people running YC don't have a chip design background, just like VCs, they learn from hearing pitches of the founders who actually know the space.

There is an obvious path forward, but apparently this is a minority opinion, possibly fringe. It doesn't make the traditional tradeoffs.

A bit level (non von Neumann) general purpose systolic array could greatly speed up AI computations, along with almost everything else. It's a chip to do general purpose computation.

The chip design is almost trivial. I'd expect someone with a few years of experience could knock it out in a few days. I hope to field a design in the next TinyTapeout (I'm on a fixed income, so I've had to wait a while)

The real problem is programming. We're talking vast greenfields that go on forever. There's no good way to target the architecture, you certainly wouldn't want to use Verilog or any other HDL.