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CapibaraZero: A cheap alternative to FlipperZero based on ESP32-S3

(capibarazero.github.io)
409 points andreock | 6 comments | 15 Oct 24 20:34 UTC | HN request time: 0.768s | source | bottom
1. snvzz ◴[16 Oct 24 04:24 UTC] No.41855590[source]▶
Cute, but I'll wait for the ESP32-P4 version (RISC-V successor to the now deprecated S line).
replies(3): >>41855687 #>>41855811 #>>41856094 #
2. auguzanellato ◴[16 Oct 24 04:44 UTC] No.41855687[source]▶
Not really a successor, they’re different chip lines (more I/O, video engine, more hardware crypto stuff but no wireless capabilities we all know and love from Espressif)
replies(1): >>41856052 #
3. readyplayernull ◴[16 Oct 24 05:10 UTC] No.41855811[source]▶
But it has no bluetooth or WIFI.
4. snvzz ◴[16 Oct 24 06:06 UTC] No.41856052[source]▶
Hmm, I had missed that. Perhaps the C line (e.g. C6) would be more suited.

Espressif CEO expressed commitment to RISC-V (now already years ago) and they've stopped releasing new chips with tensilica ISA.

As the ecosystem, toolchains and such aren't comparable to that of RISC-V and this gap will only widen, they really shouldn't be selected for new designs.

replies(1): >>41856198 #
5. asadalt ◴[16 Oct 24 06:13 UTC] No.41856094[source]▶
is S3 depeecated?
6. auguzanellato ◴[16 Oct 24 06:35 UTC] No.41856198{3}[source]▶
C line isn’t also very comparable: single (C-series) vs dual core (S3), and S3 has USB-OTG capabilities whereas C6 only has USB-JTAG.

Tensilica ESPs aren’t formally in NRND stage as of right now, for some usages they’re still the only choice, even if RISC-V is clearly the path forward.