←back to thread

SIMD < SIMT < SMT: Parallelism in Nvidia GPUs (2011)

(yosefk.com)
138 points shipp02 | 2 comments | 10 Jun 24 06:05 UTC | HN request time: 0.001s | source
Show context
HALtheWise ◴[11 Jun 24 17:27 UTC] No.40649046[source]▶
For a SIMD architecture that supports scatter/gather and instruction masking (like Arm SVE), could a compiler or language allow you to write "Scalar-style code" that compiles to SIMD instructions? I guess this is just auto-vectorization, but I'd be interested in explicit tagging of code regions, possibly in combination with restrictions on what operations are allowed.
replies(2): >>40649285 #>>40649472 #
1. doophus ◴[11 Jun 24 18:03 UTC] No.40649472[source]▶
Yes, have a look at ISPC - it's amazing. I especially like that it can generate code for multiple architectures and then select the best implementation at runtime for the CPU it's running on.
replies(1): >>40651445 #
2. xoranth ◴[11 Jun 24 21:03 UTC] No.40651445[source]▶
Do you know any good tutorial for ISPC? Documentation is a bit sparse.