SIMD < SIMT < SMT: Parallelism in Nvidia GPUs (2011)

For a SIMD architecture that supports scatter/gather and instruction masking (like Arm SVE), could a compiler or language allow you to write "Scalar-style code" that compiles to SIMD instructions? I guess this is just auto-vectorization, but I'd be interested in explicit tagging of code regions, possibly in combination with restrictions on what operations are allowed.

Check out ispc/spmd by Matt Pharr, a very interesting take on this subject

Yes, have a look at ISPC - it's amazing. I especially like that it can generate code for multiple architectures and then select the best implementation at runtime for the CPU it's running on.

Do you know any good tutorial for ISPC? Documentation is a bit sparse.