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Show HN: An LLM-Powered Tool to Catch PCB Schematic Mistakes

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55 points wafflesfreak | 2 comments | 28 Nov 25 17:30 UTC | HN request time: 0.543s | source
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swatcoder ◴[28 Nov 25 19:11 UTC] No.46081759[source]▶
Where's the performance data?

Anybody can send a PCB description/schematic into an LLM, with a prompt suggesting it generate an analysis and it will diligently produce a document that perceptually resembles an analysis of that PCB. It will do that approximately 100% of the time.

But making an LLM actually deliver a sound, useful, accurate analysis would be quite an accomplishment! Is that really what you've done? How did you know you got it right? How right did you get it?

To sell an analysis tool, I'd expect to see some kind of comparison against other tooling and techniques. General success rate? False negative rate? False positive rate? How does it do against simple schematics vs large ones? What IC's and components will it recognize and which will it fail to recognize? Does it throw an error if it encounters something it doesn't recognize? When? Do you have testimonials? Examples?

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proee ◴[28 Nov 25 19:26 UTC] No.46081918[source]▶
I'm sure your feedback is appreciated, but the tone of your reply is a skeptical engineer with arms crosses. This is a show HN post, and we should support the founder(s) if we think this is a good idea. Clearly a MVP product is not going to check all your boxes, but does it have the potential to be really useful?

I see this idea as a sort of AI ERC/DRC checker that offers some incredible opportunities. Even if it only catches one small, it could save thousand of dollars down the line.

It's another tool in the toolbox for hardware designers.

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1. achr2 ◴[28 Nov 25 19:30 UTC] No.46081969[source]▶
>> Even if it only catches one small, it could save thousand of dollars down the line.

Or it could send a design team down thousands of dollars in false positives/false negatives. With zero benchmarks provided, it is very fair to question a product that could have material negative impacts on a hardware team.

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2. proee ◴[28 Nov 25 19:36 UTC] No.46082015[source]▶
The tool would ideally classify the output into levels. Just like a compiler or DRC checker. If you submit a clean design, the tool should not be throwing major flags. 99% of the time you should be getting advisory outputs, which should not be tricking any designer. The 1% red flags should easily be understood and if you, as the designer, can't discern them, perhaps you don't understand the fundamentals of your own design.