←back to thread

Show HN: An LLM-Powered Tool to Catch PCB Schematic Mistakes

(netlist.io)
55 points wafflesfreak | 2 comments | 28 Nov 25 17:30 UTC | HN request time: 0.412s | source
Show context
proee ◴[28 Nov 25 17:47 UTC] No.46080908[source]▶
Back in the day our hardware group created a pre-flight checklist before sending boards off to fab. This reduced our errors significantly and got rid of stupid mistakes. Your product idea sounds great and has ton of opportunity for additional features like supply chain analysis, alternate part sourcing, EMC advisory, etc.
replies(2): >>46080990 #>>46085173 #
1. wafflesfreak ◴[28 Nov 25 17:56 UTC] No.46080990[source]▶
Thank you so much! Totally agree. Knowing people in the space to sanity-check designs has saved me countless times. I’m hoping this tool can bring some of that ‘pre-flight checklist’ group wisdom to solo and newer designers as well. Really appreciate the feature ideas too!
replies(1): >>46082883 #
2. throwaway31131 ◴[28 Nov 25 21:24 UTC] No.46082883[source]▶
Isn’t the primary issue that newer designers don’t know they show run ERC (or that ERC even exists)? Isn’t your tool going to have the same issue? i.e. how do user even know they should run it in the first place? How do you plan to overcome that barrier?

I’m not against more automated checkers, I’m very much for automated checkers, but I’m curious how you plan to not repeat the mistakes of the past.