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The Single Byte That Kills Your Exploit: Understanding Endianness

(pwnforfunandprofit.substack.com)
28 points andwati | 3 comments | 09 Nov 25 13:56 UTC | HN request time: 0.587s | source
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MrBuddyCasino ◴[12 Nov 25 19:51 UTC] No.45905428[source]▶
What first confused me about endianness is that it is about byte order, not bit order. The latter would have seemed more logical, or is this just me?
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jojomodding ◴[12 Nov 25 20:52 UTC] No.45906495[source]▶
You can't address individual bits. There is no way of telling if the LSBit is "left" or "right" of the MSBit. So endianness can't be about that.

For bytes, you can distinguish them, as you can look at the individual bytes produced from a larger-than-byte store.

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1. tadfisher ◴[12 Nov 25 21:36 UTC] No.45907092[source]▶
Your CPU (probably) has left and right variants for shift and rotate operations, which is certainly an avenue for confusion. There's a "logical" bit order that these operations follow, which starts with the MSBit and ends with the LSBit, even when the physical connections are all parallel and don't really define a physical bit order.
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2. NobodyNada ◴[12 Nov 25 22:09 UTC] No.45907513[source]▶
> There's a "logical" bit order that these operations follow, which starts with the MSBit and ends with the LSBit

Well, normally when bits are numbered, "bit 0" is the least significant bit. The MSB is usually written on the left, (such as for left and right shifts), but that doesn't necessarily make it "first" in my mind.

3. kazinator ◴[12 Nov 25 22:39 UTC] No.45907877[source]▶
The Common Lisp ASH (arithmetic shift) instruction has positive shifts for left, nefgative for right.

But even if machines were like this, it would not cause any interoperatibility issue. Because it is the data links between machines which ensure that bits are transmitted and received in the correct order, not the semantics of machine instructions.

It would be something to worry about when translating code from one language or instruction set to another.

Data link and physical protocols ensure that when you transmit byte with a certain decimal value like 65 (ASCII 'A') it is received as 65 on the other end.

The bits are "addressable" at the data link level, because the hardware has to receive a certain bit first, and the one after that next, and so on.