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Evaluating the Infinity Cache in AMD Strix Halo

(chipsandcheese.com)
141 points zdw | 1 comments | 22 Oct 25 04:20 UTC | HN request time: 0.234s | source
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joelthelion ◴[22 Oct 25 06:15 UTC] No.45665436[source]▶
I don't quite get it. What's so special about having 32MB of cache? Why is it called "infinity"?
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noelwelsh ◴[22 Oct 25 06:21 UTC] No.45665469[source]▶
This article from the same site goes into the Infinity Cache design in a bit more detail: https://chipsandcheese.com/p/amds-cdna-3-compute-architectur...

The summary is that it's a cache attached to the memory controllers, rather than the CPUs, so it doesn't have to worry about cache coherency so much. This could be useful for shared memory parallelism.

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1. p_l ◴[22 Oct 25 13:28 UTC] No.45668849[source]▶
IBM Power8 and Power9 used Centaur chips which had similar "last level cache" onboard.

Because it is last level before the actual ram chips, no coherency involved.