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Evaluating the Infinity Cache in AMD Strix Halo

(chipsandcheese.com)
141 points zdw | 1 comments | 22 Oct 25 04:20 UTC | HN request time: 0s | source
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joelthelion ◴[22 Oct 25 06:15 UTC] No.45665436[source]▶
I don't quite get it. What's so special about having 32MB of cache? Why is it called "infinity"?
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noelwelsh ◴[22 Oct 25 06:21 UTC] No.45665469[source]▶
This article from the same site goes into the Infinity Cache design in a bit more detail: https://chipsandcheese.com/p/amds-cdna-3-compute-architectur...

The summary is that it's a cache attached to the memory controllers, rather than the CPUs, so it doesn't have to worry about cache coherency so much. This could be useful for shared memory parallelism.

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jbreitbart ◴[22 Oct 25 12:03 UTC] No.45667781[source]▶
Since it is attached to the memory controller, one could argue that it is truly the final level of the cache hierarchy and the term infinity is not only a marketing term.
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1. ot ◴[22 Oct 25 13:18 UTC] No.45668674{3}[source]▶
But then you could add another level of slower (but still faster than RAM) and larger cache. So it is after all the CPU caches, but the first of all the memory caches. A more mathematically correct name would be L_omega.