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Diamond Thermal Conductivity: A New Era in Chip Cooling

(spectrum.ieee.org)
200 points rbanffy | 1 comments | 21 Oct 25 11:16 UTC | HN request time: 0.202s | source
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jayd16 ◴[21 Oct 25 15:29 UTC] No.45657026[source]▶
If we could stack chips, what's the theoretical density there? How thin could the layers actually be?

If a chip were to be stacked as tall as it was wide, are we talking 10x, 100x, 100,000x?

I guess for N stacks you're still paying N chips worth of wafer, and Nx the amount of defects.

replies(2): >>45657439 #>>45657689 #
1. nicktelford ◴[21 Oct 25 16:21 UTC] No.45657689[source]▶
When you use Through-Silicon Vias (TSVs) to connect the layers together, you would start to end up with scaling limits, similar to the problems of elevators in skyscrapers: the more layers you have, the higher the density of TSVs would (presumably) be required.

This is probably not an issue for thermal TSVs, because of the heat spreader layer between each silicon layer, but it would become an issue for power TSVs, as each layer would (presumably) require an independent supply of power.