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Diamond Thermal Conductivity: A New Era in Chip Cooling

(spectrum.ieee.org)
200 points rbanffy | 1 comments | 21 Oct 25 11:16 UTC | HN request time: 0.199s | source
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jayd16 ◴[21 Oct 25 15:29 UTC] No.45657026[source]▶
If we could stack chips, what's the theoretical density there? How thin could the layers actually be?

If a chip were to be stacked as tall as it was wide, are we talking 10x, 100x, 100,000x?

I guess for N stacks you're still paying N chips worth of wafer, and Nx the amount of defects.

replies(2): >>45657439 #>>45657689 #
1. wtallis ◴[21 Oct 25 16:02 UTC] No.45657439[source]▶
NAND flash memory chips these days are manufactured with low hundreds of layers of memory cells on each die, so they're probably some of the thickest individual dies. They are commonly packaged with up to 16 dies per package, usually in one or two stacks. Those packages are usually under 3mm thick.

The packaging usually has the stacked dies offset in a staircase pattern so that the contacts at the edge are exposed for every die. The alternative is through-silicon vias (TSVs), which theoretically would allow stacking until you have a mass of chips that is roughly a cube, but achieving that without having a defective connection somewhere in the stack is approximately impossible.