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The world has a running Rational R1000/400 computer again (2019)

(datamuseum.dk)
53 points MaxLeiter | 1 comments | 07 Sep 25 02:46 UTC | HN request time: 0s | source
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phkamp ◴[07 Sep 25 05:11 UTC] No.45155578[source]▶
The R1000 is a micro-coded computer built from approx 5k TTL functions, with an instruction set consisting of Ada Primitives like "Define a type for a variant structure with 3 variants, you'll get the details later".

It processes 64bit data and 64 bit type information about that data in parallel, in hardware.

It is also object oriented in hardware, there is no linear address space or VM-tree,

Three left in the world, plus one mostly empty chassis.

My Covid19 project was writing a software emulation of it, starting from 400 pages of schematics, because the instruction set is not documented.

And yes, I'm way behind on documenting it, because I also have a life :-)

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quietbritishjim ◴[07 Sep 25 07:57 UTC] No.45156298[source]▶
> instruction set consisting of Ada Primitives like "Define a type for a variant structure with 3 variants, you'll get the details later".

Wow, it's hard for me to imagine a CPU with such high level instructions. Were these per-process, like virtual memory on a modern processor? Or was there only expected to be one executable running on the machine at a time?

> My Covid19 project was writing a software emulation of it,

Where did you get to? Do you have a link?

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TheOtherHobbes ◴[07 Sep 25 15:07 UTC] No.45158840[source]▶
The microcoding means you have fairly standard CPU hardware - an ALU, some registers, memory ports, and so on - and the microcode sequences it to emulate the ISA.

So it's not that the ADA primitives were baked directly into TTL.

It's somewhat related to the Itanium model where the compiler generates a Very Long Instruction Word.

Microcode is a standard way of implementing CISC, but this machine took it further than usual.

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1. phkamp ◴[07 Sep 25 16:26 UTC] No.45159622[source]▶
"fairly standard" is a bit of an understatement in this particular case.

The machine actually has both an ALU as we know it, called the "VAL" board, but it also has a second unit, which runs in parallel on the "TYP" board, which does checks and operations on the data types of the data on the VAL board.

That means that the compiler can just emit a "ADD" instruction, and leave it to the microcode to figure out if it is adding two floating point numbers, two integers or a floating-point plus an integer and if the numeric type has a range, the result will be checked to fit inside that range.

So the comparison to the Itanic is not helpful. Itanic was a pretty standard CPU which forced a lot of constraints and complexity into the compiler.

The R1000 does the opposite: The compiler gets to emit code which operates on the types as the Ada language defines and knows them, and the hardware+microcode translates that into action.

Grady Booch donated some internal documents to us, and they contain a couple of references to "Incredibly Complex Instruction Set Computer" and they're not half wrong about that.