←back to thread

Condor's Cuzco RISC-V Core at Hot Chips 2025

(chipsandcheese.com)
155 points rbanffy | 1 comments | 30 Aug 25 14:18 UTC | HN request time: 0.212s | source
Show context
bee_rider ◴[30 Aug 25 15:20 UTC] No.45075394[source]▶
The static schedule part seems really interesting. They note that it only works for some instructions, but I wonder if it would be possible to have a compiler report “this section of the code can be statically scheduled.” In that case, could this have a benefit for real-time operation? Or maybe some specialized partially real-time application—mark a segment of the program as desiring static scheduling, and don’t allow memory loads, etc, inside there.
replies(4): >>45075641 #>>45075901 #>>45078349 #>>45087597 #
usrusr ◴[30 Aug 25 15:50 UTC] No.45075641[source]▶
What would the CPU do with the parts not marked as "can be statically scheduled"? I read it as they try it anyways and may get some stalling ("replay") if the schedule was overoptimistic. Not sure how a compiler marking sections could be of help?
replies(2): >>45075909 #>>45081427 #
imtringued ◴[31 Aug 25 08:18 UTC] No.45081427[source]▶
Assuming a parallel programming language and a SMT aware compiler, the CPU could just switch to another block of static instructions while it is waiting.
replies(2): >>45082184 #>>45087612 #
1. namibj ◴[31 Aug 25 22:17 UTC] No.45087612[source]▶
You mean like e.g. Nvidia Maxwell?

(There's decent 3rd party documentation from nervana systems from when they squeezed all they could out of f32 dense matrix multiply, at the time substantially faster than Nvidia's cuBLAS library; this is very not exclusive to that architecture, though.)