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125 points todsacerdoti | 2 comments | | HN request time: 0.014s | source
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gwd ◴[] No.45038833[source]
Kind of weird that NOP actually slows down the pipeline, as I'd think that would be the easiest thing to optimize out of the pipeline, unless instruction fetch is one of the main limiting factors. Is it architecturally defined that NOP will slow down execution?
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Someone ◴[] No.45039234[source]
I think it would be easy, but still not worth the transistors. Think of it: what programs contain lots of NOPs? Who, desiring to write a fast program, sprinkles their code with NOPs?

It’s not worth optimizing for situations that do not occur in practice.

The transistors used to detect register clearing using XOR foo,foo, on the other hand, are worth it, as lots of code has that instruction, and removing the data dependency (the instruction technically uses the contents of the foo register, but its result is independent of its value) can speed up code a lot.

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1. adrian_b ◴[] No.45039617[source]
On CPUs with variable instruction length, like the Intel/AMD CPUs, many programs have a lot of NOPs, which are inserted by the compiler for instruction alignment.

However those NOPs are seldom executed frequently, because most are outside of loop bodies. Nevertheless, there are cases when NOPs may be located inside big loops, in order to align some branch targets to cache line boundaries.

That is why many recent Intel/AMD CPUs have special hardware for accelerating NOP execution, which may eliminate the NOPs before reaching the execution units.

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2. kevin_thibedeau ◴[] No.45042976[source]
MIPS required NOP insertion for data hazards and the branch delay slot if a productive instruction couldn't be placed in the slot.