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420 points speckx | 2 comments | | HN request time: 0.414s | source
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GeekyBear ◴[] No.44533662[source]
The article speculates on why Apple integrates the SSD controller onto the SOC for their A and M series chips, but misses one big reason, data integrity.

About a decade and a half ago, Apple paid half a billion dollars to acquire the patents of a company making enterprise SSD controllers.

> Anobit appears to be applying a lot of signal processing techniques in addition to ECC to address the issue of NAND reliability and data retention. In its patents there are mentions of periodically refreshing cells whose voltages may have drifted, exploiting some of the behaviors of adjacent cells and generally trying to deal with the things that happen to NAND once it's been worn considerably.

Through all of these efforts, Anobit is promising significant improvements in NAND longevity and reliability.

https://www.anandtech.com/show/5258/apple-acquires-anobit-br...

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jeffbee ◴[] No.44533738[source]
> Through all of these efforts, Anobit is promising significant improvements in NAND longevity and reliability.

Every flash controller does this. Modern NAND is just math on a stick. Lots and lots of math.

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dontlaugh ◴[] No.44533804[source]
Presumably Apple want to be able to guarantee the quality of such logic.

Still sucks that you can’t use standard parts.

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jeffbee ◴[] No.44533956[source]
Sure, and I agree with that goal. In fact I would like NVMe controllers to simply not exist. The operating system should manage raw flash, using host algorithms that I can study in the the source code.
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1. gruturo ◴[] No.44534146[source]
I'm with you, but.... no. At the level where the controller is operating, things are no longer digital. Capacity (as in farads, not bytes), voltage, crosstalk, debouncing, traces behaving like antennas, terminations, what have you. Analog values, temperature dependencies, RF interference. Stuff best dealt with custom logic placed as close as possible to it.
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2. jeffbee ◴[] No.44535438[source]
The physical interface controller can exist to that extent, of course. But I think the command interface it should present to the host system should be a physical one, not a logical translation. The host should be totally aware of the layout of the flash devices, and should command the things that the devices are actually capable of doing: erase this, write that, read this.

We already see the demand for this in the latest NVMe protocol spec that allows the host to give placement hints. But this is a half-measure that suggests what systems really want, which is not to vaguely influence the device but instead to tell it exactly what to do.