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Upgrading an M4 Pro Mac mini's storage for half the price

(www.jeffgeerling.com)
420 points speckx | 2 comments | 11 Jul 25 14:06 UTC | HN request time: 0.501s | source
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GeekyBear ◴[11 Jul 25 15:55 UTC] No.44533662[source]▶
The article speculates on why Apple integrates the SSD controller onto the SOC for their A and M series chips, but misses one big reason, data integrity.

About a decade and a half ago, Apple paid half a billion dollars to acquire the patents of a company making enterprise SSD controllers.

> Anobit appears to be applying a lot of signal processing techniques in addition to ECC to address the issue of NAND reliability and data retention. In its patents there are mentions of periodically refreshing cells whose voltages may have drifted, exploiting some of the behaviors of adjacent cells and generally trying to deal with the things that happen to NAND once it's been worn considerably.

Through all of these efforts, Anobit is promising significant improvements in NAND longevity and reliability.

https://www.anandtech.com/show/5258/apple-acquires-anobit-br...

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jeffbee ◴[11 Jul 25 16:00 UTC] No.44533738[source]▶
> Through all of these efforts, Anobit is promising significant improvements in NAND longevity and reliability.

Every flash controller does this. Modern NAND is just math on a stick. Lots and lots of math.

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dontlaugh ◴[11 Jul 25 16:06 UTC] No.44533804[source]▶
Presumably Apple want to be able to guarantee the quality of such logic.

Still sucks that you can’t use standard parts.

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jeffbee ◴[11 Jul 25 16:17 UTC] No.44533956[source]▶
Sure, and I agree with that goal. In fact I would like NVMe controllers to simply not exist. The operating system should manage raw flash, using host algorithms that I can study in the the source code.
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1. nine_k ◴[11 Jul 25 16:30 UTC] No.44534134[source]▶
How do you think it would be electrically connected to the CPU?

Same thing with DDR5: the electrical layer is a beast, it's a reason enough to require its own controller.

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2. daneel_w ◴[11 Jul 25 16:43 UTC] No.44534262[source]▶
> How do you think it would be electrically connected to the CPU?

On the CPU's PCIe bus. NVMe drives are PCIe devices, designed specifically to facilitate such interfacing.

Edit: Pardon, misread the actual statement you responded to. Of course one shouldn't hook NAND directly to the CPU. I'll leave my response for whatever value the info has.