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42 points LorenDB | 2 comments | | HN request time: 0.668s | source
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snvzz ◴[] No.44374852[source]
Great project, but emphasis on Almost[0].

It will not work in the one computer where I need it; On Haswell, 32GB RAM + 16GB BAR is currently not possible[1].

0. https://github.com/xCuri0/ReBarUEFI/wiki/Common-issues-(and-...

1. https://github.com/xCuri0/ReBarUEFI/issues/20

replies(1): >>44375855 #
p_l ◴[] No.44375855[source]
From my understanding consumer sandy bridge<->broadwell line was "cursed" when it came to memory controller in general, including flat out not supporting DDR3 spec in full (multiple versions being physically incapable of generating control signals for certain standard-compliant DDR3 modules)
replies(1): >>44383137 #
1. snvzz ◴[] No.44383137[source]
That sounds pretty bad, as it's 4.5 generations (sandy/ivy bridge, haswell+refresh and broadwell).

Fortunately, it doesn't matter anymore; Moved that 7900gre to my new machine (Ryzen 9800x3d + 2x 48G DDR5 w/ECC).

replies(1): >>44385342 #
2. p_l ◴[] No.44385342[source]
As far as I know, the memory controller IP on the die, as in the part actually interacting with DDR3 channels, didn't change much over that time.

And not including support for bigger ranks probably saved some amount of circuitry or allowed higher speed, just like moving permission checks to happen last before writeback in the CPU core :|