PCBs, copper pours, ground planes, and you

There are a lot of things getting mixed up here: ground planes for EMC, ground planes for electrical performance, ground planes for DFM/etching, and ground planes as "fashion".

First off, let's just say that meeting radiated EMC ("47 CFR Part 15" according to the article, equivalent to CISPR 22/32 in Europe) is a bloody good idea. Yes, the testing labs are "a bit of a racket". But does anyone else remember the days when turning on the vacuum cleaner would knock out the TV? That wasn't great. And we have a whole lot more electronics in the world today. A world without Part 15/CISPR is an ugly world indeed.

Four-layer boards are cheap. Really cheap. They may be double the cost, but you're doubling pennies here. In fact, just checking in with one common low-volume supplier, they're not doubling: the price for 200mm × 100mm boards with good specs goes from $9.34 each in quantity 10 to... $10.59. For prototypes, that's basically a rounding error. Perhaps even literally a rounding error. So don't complain about the cost of four-layer boards anymore, it isn't 2004.

Internal ground fill layers are what people usually mean when talking about "ground planes". They have three key properties:

1. They are very easy to do and are very tolerant of mistakes. You don't have to calculate return current paths, you don't have to size and locate return current traces, you don't have to gum up your routing. You just dedicate the layer and it works, and it keeps working if you have to make changes later.

2. They help shield internal layers further down in the stack from radiating. This is usually minor, but for nasty digital stuff or high-power electronics, can be useful.

3. They develop inter-plane capacitance with nearby power layers, if inter-layer dielectrics are small. This is critical to maintaining power distribution network performance at high frequencies (>100s of MHz). This stuff is very, very important to make high-speed digital logic work well. Of course, it's only one link in the chain (GHz stuff gets handled on-package or even on-die; <100MHz is the job of on-board capacitors until you get into power supply dynamics in the kHz and below). This is the "increasing shunt capacitance" mentioned in the article. Yes, it can be bad news for analog stuff, but this is both very rare and the sort of problem where anyone who can do that kind of difficult analog design has the skill to punch a hole in the plane where it's needed.

There is also a manufacturing issue where the manufacturers find it easiest to have approximately balanced amounts of copper on opposite layers of a board. Copper pours are one solution to this. Copper thieving pads are another. This is important but easy to manage, and vendors are good at it.

So all of the above applies to internal layer copper fills. None of it is "fashion": there are good reasons to do it, the extra layers are cheap these days, and it's an easy and robust way to design things. Fills on external layers are a different matter; they're kind of stupid in a lot of cases. Unless you're doing a two-layer design, or a 4-layer that kind of ends up behaving like a 2-layer (this happens sometimes when stuff is very tight), the external fills are pretty worthless. I wrote more about this ages ago over here: https://www.eevblog.com/forum/eda/altium-article-on-never-us... This is the only real thing I'd agree with the article on.

There's a lot of stuff going on here, and I don't think this article does a very good job keeping it straight. If you take one thing away from all of this, it should probably be that internal copper planes are pretty great, and what happens on the outside of the board isn't so important.

The default should be X / GND / X GND to maintain tight coupling of both signals and power to the GND plane and stitch the GND planes together with vias close to any other via that changes layers to maintain return paths.

Power should be routed normally, except it should use widest practical traces and get decoupled with C close to ICs that consume it.

But in any case, you always need to think about the signal and return. Even for power. It's never truly DC.

If you do the "classic" signals / GND / VDD / signals, you are routing over VDD plane and your ground is waaay farther. Means all accidental VDD noise (you can't pinpoint, because it takes frequency dependent paths across the VDD/GND C) gets coupled into your signals on the back side.

So don't do that.

The standard configuration, with a "fat core", is pretty much the best you can do in 4 layers for a "modern" design. By "modern" I mean something with a dense component load, probably double-sided load, and random-ish routing (so, exactly the opposite of the old '80s TTL design shown in the article image we're discussing in sibling comment). All the "better" 4-layer stackups require outer layers to be doing a lot of heavy lifting, which they cannot do if they are filled with parts. When you assume they have to be filled with parts -- because if they aren't filled with parts then I can make it smaller and people want that! -- then you just cannot use that space as anything else. Henry Ott discusses a number of stackup options for four layers, and the standard one is the only option of his that survives with this restriction. If you don't like that, tough, I guess you're paying for 6 or 8 layers. Which isn't too bad these days!

You complain about power (VDD) plane noise. This might be important in ultra-low-noise design, I don't know, I try not to do that sort of work. In normal work it is not a factor. Your power and ground planes should be connected by a pretty thick network of capacitors, so they are transparent to each other. Your power plane is as good as a ground plane for AC, and AC is the only thing that's hard to deal with. So there is no issue routing the bottom layer on the other side of power, not ground. (Of course, that is no longer true if your power plane is split. Split power planes in a high-speed 4-layer design can be nasty, and are how I justify my worth to my employers!)

I've also heard, possibly apocryphally, that in the old days when we used harsher chemical etchants, removing all of the copper from unused sections of the PCB would increase the risk of thinning the traces beyond what was intended. So in those cases a copper pour would reduce the time the PCB would need to spend in the etchant bath.

If you put the power planes on the inner layers and the signal on the outer layers, it's much easier to visually inspect the signal layers. And if you got something wrong on the prototype and you have to fix it manually, the traces are right there where you can get at them.

On the other hand, if you're doing some performance-critical RF wizardry, you might put the ground planes on the outer layers and the signal on the inner layers, sandwiching your signal between two ground planes. So if you look at a wifi module or something like that, sometimes the outer layers will have very few traces.

And then this article totally ignores solid metal PCBs, which are my realm of specialty and have their own inherent challenges when it comes to digital equipment.

Rick Hartley explains.

Or really, the default today is a 6 layer board because 4 is still kinda bad.

Today's engineers know that signal-top has a return path through ground-top. But if you ever were to via a wire from signal-top to signal-bottom, the return path gets lost (aka: return path is now through the board or worse, through the air and radiating off of your board).

To prevent this erratic behavior, you must continue to think about the return path and tie a via from ground-top to ground-bottom as close as possible to the via between signal-top and signal-bottom.

--------

6 layer can do signal/ground/signal -core- signal/ground/signal

Where core is the FR4 material (keeping the middle signals far enough apart that they likely don't interfere with each other). This allows vias between layer#1 and #3 without needing a secondary return via. (But if you need layer#1 to layer#6 via, then the previous advice still applies where ground-top needs a secondary return via to ground-bottom).

Even if a board is double-sided, it is common to avoid putting major ICs on both sides, unless the space constraints are severe. Often, people will only put passive components on the bottom side.

I believe you are trying to get a stackup that supports use of stripline for signals. That is a reasonable goal but it is only appropriate for very high speed digital designs. If you route stripline on a regular basis, you're either very experienced or clueless. No middle ground!

Really, for heavy-duty work, you need six. And you can argue with me, and say that by great skill you can get things into four layers, and that is true. But six-layer boards are cheap compared to what they used to be, so for anything not going into true high-volume manufacturing, just go for six or eight. In all other cases, the design cost hit will outweigh the parts cost savings.

A great app note on getting started with thermal design from TI: https://www.ti.com/lit/an/snva183b/snva183b.pdf

https://resources.altium.com/p/2-the-extreme-importance-of-p...

That AC signal energy is contained in the field between the trace and it's return is such a powerful model compared to taking the DC model of "going the lowest impedance path" and just assuming it applies at AC. Very, very, very good talk.

This model also automatically makes clear why you'd want signal-GND-GND-signal instead of a power plane because that side's signals will have coupling into the power plane. It is mentioned explicitly in the video as well.

So preferring a fourth signal layer before adding a power layer?

Power planes are overrated especially for 100mA designs. If you are running a 500Amp GPU obviously you should consider a power plane but what kind of designs are people doing here?

EDIT: 10 Amp on 1oz according to first trace width calculator is supported by 20mm or 300 mil trace width. There's no reason to have a full power plane on amperage grounds.

And if you need board capacitance for your design to work then yeah, Power Planes can be useful for that. But only the highest of frequency circuits (think GHz+) seem to require those.

And if you do use Power Planes, then return currents may be induced on the Power plane instead of the ground plane, which is bad and hard to think about. (Power Planes cannot be shorted to Ground, meaning your return current needs to go across a high inductance via, into a capacitor, through to the ground plane where the return current should have been in the first place).

---------

Basically, power planes are one of those things that work at 50MHz just fine (enough random capacitors that magically transfer signals to the ground plane). But much above that frequency and those capacitors look more like a parasitic inductor. 500MHz signals will NOT go through a 100nF 0402 cap, that thing is practically an indicator by those frequencies. So it's not like power planes are easy to use.

The people who 'Need' a power plane are doing far more complex designs than the vast majority of board designers. And if they really need it, then they are using complex FEA simulations and calculations of PDNs that far exceed the scope of the level of advice in this topic.

If anyone’s curious, you can check it out here: capext.com

I mixed up internal vs external trace width here.

700mil or 20mm internal trace.

300mil or 8mm external trace.