The article misses the real reason why pours were uncommon in the 80s, which is that people had to actually “tape out” the whole thing, and it was very annoying to do pours that way.
In any case, if you have to add the top layer pour, make sure to:
1. Use high clearence so as not to introduce edge coupling that changes your carefully calculated trace impedance.
2. Stitch the pour to actual GND with vias. Thoroughly. Do not let it float.
You do calculate trace impedance, right? :-)
I am only half joking. Some components let you specify source impedance. RP2040 has GPIO drive strength in mA, but they roughly correspond to 12 mA / 33 Ohm, 8mA / 50 Ohm, 4 mA / 70 Ohm and 2 mA / 100 Ohm. I usually use 100 for 2 layer boards and 70 for 4 layer boards. This is effectively series termination.
It seems to depend on the design - how close you are to the design limits and how much copper is exposed on the outer layers.
A message someone got from JLC for an open source project recently:
> When the copper pour is less than 30% of board area, we suggest to keep at least 0.15mm trace spacing.
> Or the dry film debris might have chance make short circuit, it will make quality control more difficult