Branchless UTF-8 Encoding

>So on x86_64 processors, we have to branch to say “a 32-bit zero value has 32 leading zeros”. Put differently, the “count leading zeros” intrinsic isn’t necessarily a branchless instruction. This might look nicer on another architecture!

Yes, RISC-V for example defines the instructions for counting leading / trailing zeros (clz, clzw, ctz, ctzw) such that an N-bit zero value has N of them.

I don't know if I can show it on Rust Godbolt because none of the default RISC-V targets that Rust has support the Zbb extension, but I checked with a custom target that I use locally for my emulator, and `leading_zeros()` indeed compiles to just one `clz` without any further branches. Here's a C demonstration though: https://gcc.godbolt.org/z/cKx3ajsjh

Due to AMD, the x86-64 ISA has been corrected several years before the birth of RISC-V (in 2007).

The 32-bit ARM ISA also had CLZ many years before RISC-V.

IBM POWER had the correct instruction since 1990.

The mnemonic LZCNT comes from Cray-1 (1976), but similar instructions had already existed even in some of the first computers with vacuum tubes.

Few computer ISAs except 80386 (where these had mistaken definitions, while also using mnemonics not encountered elsewhere: BSF and BSR) have included both LZCNT and TZCNT, but many have included at least 1 of them.

LZCNT has been much more widespread, because it is more useful (allowing both the computation of the integer part of the base 2 logarithm of an integer number and of TZCNT, when that is desired), but DEC VAX has been one of the few that had only the equivalent of TZCNT (though VAX also had "FFC", find first clear bit, i.e. first zero bit after a string of "1", starting from the LSB).