Be Aware of the Makefile Effect

Someone remind me, is it $@ or $< ?

For what?

In a given rule:

    foo.o : foo.c
            $(CC) $(CFLAGS) -o $@ $<

The "$@" is the output (or target, think of @ as a bullseye on a target), and the "$<" is the input (think redirection). The only other commonly used variable is "$^":

    foo : foo.o util.o other.o
            $(CC) $(LDFLAGS) -o $@ $^ $(LDLIBS)

In this case, "$^" means "all inputs".