This is reality in VLSI CAD.
Now you understand why everything in hardware engineering is stupidly dysfunctional.
We don't need "shift left". We need tools that don't cost a megabuck.
The problem is that we don't really need more digital. Digital is covered--there is a 99% probability that you can abuse somebody's microcontroller to do what you need if what you need is digital.
That isn't true if your need is analog or RF. If the thing you need is even slightly off the beaten path, you're simply out of luck.
The big problem with those right now is DRC (design rule checking), LVS (logical vs schematic), and parasitic extraction. Magic wasn't even good back in the 90s, and technology moving forwards has simply made it even less good.
The issue is that funding for the open source EDA stuff mostly comes from the US DoD, and the US DoD is only funding all this because they want to somehow magically make digital hardware design a commodity so that their projects somehow magically get cheaper.
The problem, of course, is that the primary reason US DoD chip runs are so damn expensive is that they are stupidly low volume so all the NRE costs dominate. Even worse, everybody in government contracting knows that your funding is whimsical, so you frontload the hell out of everything to minimize your funding risk. So, you have big upfront costs multiplied by a big derisking factor.
The real solution would be for the DoD to pull this stuff in house somewhere--software, design and manufacturing. But that goes against the whole "Outsource All The Things(tm)!" mantra of modern US government.
The existing open PDKs are for technologies from 20 years ago.
If TSMC, Intel, Samsung, or even Global Foundries or other second tier foundry would publish the design rules for their manufacturing processes and specifications of the formats for the product documentation that they must receive from a customer, it would be easy to make something better than the overpriced commercial tools.
I have used for many years the tools provided by Cadence, Mentor and Synopsys, so I know with certainty that it would be easy to improve on them if only one would have access to the documents kept secret by TSMC and the like.
This collusion of the foundries with the EDA vendors that eliminates the competition from the EDA market does not make much sense. Normally better and cheaper design tools should only bring more customers to the foundries, so I do not understand what do they gain from the status quo. (Unless they fear that public documentation could make them vulnerable to litigation from patent trolls.)
Fear of competition in the foundry market cannot be the reason for secret design rules. There is negligible competition in the foundry market and the most dangerous competitor of TSMC is Intel. Yet TSMC makes now chips for Intel, so the Intel designers have seen much of the TSMC design rules and they could chat about them with their buddies from the Intel foundry division. So TSMC must not give great importance in keeping the design rules secret from direct competitors. Therefore they must keep the rules secret mainly for other parties, but I cannot guess who are those.
What the foundries gain isn't clear, but they have more customers lined-up than they can serve, so they don't lose anything to it.
I am not sure that they have more business than they know what to do with, esp at larger node sizes. Most foundries are forever stuck at what their current node is. 40nm is still plenty good for the majority of long tail ICs.