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A programmable FPGA SoM in the tiny microSD form factor

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90 points LorenDB | 1 comments | 15 Nov 24 13:48 UTC | HN request time: 0.211s | source
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mattofak ◴[15 Nov 24 23:46 UTC] No.42152635[source]▶
This sounds fun to play with and get feet wet in HDL, but it's only a lattice ice40, I have no idea what you'd seriously do with this. Usually ice40 are used as glue logic, or multiplexing/buffering a bunch of ADC/DAC chips so the processor can do large data transfers instead of a bunch of tiny ones.

The website claims hardware acceleration and... I doubt they got timing closure on the soft CPU at anything greater than 100MHz and you still have to get data to/from it at likely 30~40 MB/s via an SDMMC bus.

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ruslan ◴[16 Nov 24 02:18 UTC] No.42153566[source]▶
Lattice's FPGAs are very nice. With an iCE40 you can have a full featured RISC-V soft-core (RV32IMFAC) at some 80 MHz.
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1. wyager ◴[18 Nov 24 20:56 UTC] No.42176920[source]▶
For a lot of the iCE40 chips, it's extremely difficult to reliably get fMax > 50MHz even with extremely aggressive pipelining. I assume 80MHz is only possible on the highest-speed parts in the iCE40 family

I switched a design from iCE40 to ECP5 and got a ~3x speedup "for free"

Agreed that using Lattice FPGAs is super nice, mostly because you get to use the open-source Yosys toolchain, which is vastly better than proprietary toolchains IMO