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63 points trelane | 1 comments | | HN request time: 0.21s | source
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dusted ◴[] No.42166600[source]
it just dawned on me how trivially simple it would be for memory controllers to implement ECC in UDIMMs, for every N words, reserve 1 word for parity. You gain ECC for a small decrease in capacity. Since the memory controller is on the CPU, it can easily abstract this away.
replies(2): >>42166695 #>>42173924 #
1. sliken ◴[] No.42173924[source]
Nvidia GPUs, that support ECC, do this. I believe it's called inline ECC and does cost latency, bandwidth, and memory capacity.

This helps, but ideally the entire path from CPU to Dimms is wider and covers not just what is being read or written, but also the address it's being written to. After all writing the correct bits to the wrong address is a serious failure.