DIMM vs. Udimm vs. Rdimm vs. Sodimm vs. Cudimm: What's the Difference?

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63 points trelane | 1 comments | 17 Nov 24 05:31 UTC | HN request time: 0.209s | source

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dusted ◴[17 Nov 24 19:53 UTC] No.42166600[source]▶

it just dawned on me how trivially simple it would be for memory controllers to implement ECC in UDIMMs, for every N words, reserve 1 word for parity. You gain ECC for a small decrease in capacity. Since the memory controller is on the CPU, it can easily abstract this away.

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kvemkon ◴[17 Nov 24 20:04 UTC] No.42166695[source]▶

>>42166600 #

Indeed. Intel has recently implemented it in a low-cost CPU SoC: "in-band ECC".

https://news.ycombinator.com/item?id=41090956

But you not only loose some capacity. Some bandwidth is also lost. And perhaps even some CPU cycles, since likely in-band ECC hasn't been implemented purely in a hard IP-block.

replies(1): >>42167425 #

wtallis ◴[17 Nov 24 21:23 UTC] No.42167425[source]▶

>>42166695 #

I think the bigger performance problem is that a read burst from one channel of RAM is no longer matched to the CPU cache line size when doing in-band ECC.

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1. dusted ◴[18 Nov 24 06:40 UTC] No.42170293[source]▶

>>42167425 #

This is true, however, with the readahead cpu's usually do anyway, I don't even think it's that bad.. There is definitely a performance and capacity cost, but again, technically, that capacity cost is also present in ECC memory, that extra memory is still there, it's just not printed on the label, and instead, the stick is more expensive..

The cpu cache won't be mismatched though, since the memory controller can mask this. The performance hit will be due to the memory controller having to do the extra reads for parity.

That will be a tiny mismatch, and I wonder if the performance implication of this won't more or less be equal to the performance difference we already have between buffered and unbuffered memory (more or less the same, simply, now that "extra work", moved from inside the dimm, to the memory controller)

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