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YC is wrong about LLMs for chip design

(www.zach.be)
317 points laserduck | 1 comments | 16 Nov 24 14:07 UTC | HN request time: 0.209s | source
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lizknope ◴[16 Nov 24 23:31 UTC] No.42160518[source]▶
I've been designing chips for almost 30 years.

We have a bunch of AI initiatives in my company but most of them are about using Copilot to help write scripts to automate the design flow. Our physical design flow are thousands of lines of Tcl and Python code.

The article mentions High Level Synthesis. I've been reading about this since my first job in the 1990's. I've worked on at least 80 chips and I've never seen any chip use one of these tools except for some tiny section that was written by some academics who didn't want to learn Verilog for reasons.

replies(1): >>42165627 #
1. shash ◴[17 Nov 24 17:54 UTC] No.42165627[source]▶
I've never tried SystemC. But after having tried to learn Chisel and friends, and successfully learning Bluespec (and using it in professional projects), I have some insights.

It's fundamentally important when doing hardware design to work in a language that _expresses_ itself like you're designing hardware. Verilog (for all its faults) shines there because it feels like you're writing a slightly higher level netlist. That's not the case with SC and friends, which doesn't allow you to think in hardware. Languages like BSV and SV are functionally similar but they force you to think in similar ways to Verilog, meaning you can write much tighter high-level code.

I'd be interested in your experience, but I feel that using normal programming languages to build hardware is an abstraction failure. Which is why it performs so poorly.