YC is wrong about LLMs for chip design

(www.zach.be)

317 points laserduck | 1 comments | 16 Nov 24 14:07 UTC | HN request time: 0.216s | source

1. h_tbob ◴[17 Nov 24 00:04 UTC] No.42160724[source]▶

I wonder if it’s because llm doesn’t have access to state of the art Verilog?

I mean I assume the best is heavily guarded.