Plenty of people are commenting on how modern microcontrollers are better than the 555. I agree, with a caveat: the 555 is a great learning tool. It is complex enough to be interesting, yet simple enough to be well understood. It is easy to clip an oscilloscope to it's pins to have a visual representation of how its inputs affects its outputs. It is a stepping stone that helps people learn how to build more complex circuits. Much as some software developers have to understand assembly language to build the most fundamental bits of software (e.g. compilers), some people have need to understand electronics to build the most fundamental bits of hardware.
I always found DACs/IO to be the limiting thing with microcontrollers. That and latency in general. When you were doing analog stuff with op-amps, yeah, you were setting yourself up for other problems like thermal drift, but there was never any worry that you were going to run out of capacity like you would switching tasks on a microcontroller, and latency was negligible. Plus there weren't many wires and you could see it on a scope. It was all satisfyingly immediate. I wonder what kind of cheap and ubiquitous DSPs(?) people use for that kind of niche nowadays, to do it digitally(?). Do they string DACs together on a bus somehow? How do you get, say, signals flowing around at a couple hundred kHz sample rates, with nice dataflow parallelism -- and then get those signals out to actuators, without much latency -- in that world? Like, what would you use to mix a bunch of audio and run some IIR filters with 20ns latency? Or control, say, four motors with, I dunno, 1 kHz bandwidth? I get this feeling that DACs remain a bottleneck and you're rapidly looking at expensive stuff to do that with a microcontroller, but maybe I'm wrong; I don't do this stuff.
As an FPGA developer: much agreed. We know exactly what's happening every clock cycle (or at least can), and often are able to have extremely deterministic computation. You can do this on micros, but anything with good performance will have some caching, maybe context switching, etc. The polarfire SoC marketing has a graph showing either determinism or performance (I can dig it up if interested). In FPGA land, we define the pipelining such that we get both. I usually go out to an RFIC then stop caring, but you can calculate the latencies the as well.