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486 points dbreunig | 1 comments | | HN request time: 0s | source
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jsheard ◴[] No.41863390[source]
These NPUs are tying up a substantial amount of silicon area so it would be a real shame if they end up not being used for much. I can't find a die analysis of the Snapdragon X which isolates the NPU specifically but AMDs equivalent with the same ~50 TOPS performance target can be seen here, and takes up about as much area as three high performance CPU cores:

https://www.techpowerup.com/325035/amd-strix-point-silicon-p...

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Kon-Peki ◴[] No.41863880[source]
Modern chips have to dedicate a certain percentage of the die to dark silicon [1] (or else they melt/throttle to uselessness), and these kinds of components count towards that amount. So the point of these components is to be used, but not to be used too much.

Instead of an NPU, they could have used those transistors and die space for any number of things. But they wouldn't have put additional high performance CPU cores there - that would increase the power density too much and cause thermal issues that can only be solved with permanent throttling.

[1] https://en.wikipedia.org/wiki/Dark_silicon

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IshKebab ◴[] No.41864171[source]
If they aren't being used it would be better to dedicate the space to more SRAM.
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a2l3aQ ◴[] No.41864316[source]
The point is parts of the CPU have to be off or throttled down when other components are under load to maintain TDP, adding cache that would almost certainly be being used defeats the point of that.
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1. IshKebab ◴[] No.41866947[source]
Cache doesn't use nearly as much power as active computation; that was my point.