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Box64 and RISC-V in 2024: What It Takes to Run the Witcher 3 on RISC-V

(box86.org)
366 points pabs3 | 2 comments | 27 Aug 24 04:23 UTC | HN request time: 0.57s | source
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Manfred ◴[27 Aug 24 08:31 UTC] No.41365540[source]▶
> At least in the context of x86 emulation, among all 3 architectures we support, RISC-V is the least expressive one.

RISC was explained to me as a reduced instruction set computer in computer science history classes, but I see a lot of articles and proposed new RISC-V profiles about "we just need a few more instructions to get feature parity".

I understand that RISC-V is just a convenient alternative to other platforms for most people, but does this also mean the RISC dream is dead?

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gary_0 ◴[27 Aug 24 09:09 UTC] No.41365687[source]▶
As I've heard it explained, RISC in practise is less about "an absolutely minimalist instruction set" and more about "don't add any assembly programmer conveniences or other such cleverness, rely on compilers instead of frontend silicon when possible".

Although as I recall from reading the RISC-V spec, RISC-V was rather particular about not adding "combo" instructions when common instruction sequences can be fused by the frontend.

My (far from expert) impression of RISC-V's shortcomings versus x86/ARM is more that the specs were written starting with the very basic embedded-chip stuff, and then over time more application-cpu extensions were added. (The base RV32I spec doesn't even include integer multiplication.) Unfortunately they took a long time to get around to finishing the bikeshedding on bit-twiddling and simd/vector extensions, which resulted in the current functionality gaps we're talking about.

So I don't think those gaps are due to RISC fundamentalism; there's no such thing.

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Closi ◴[27 Aug 24 10:04 UTC] No.41365919[source]▶
Put another way, "try to avoid instructions that can't be executed in a single clock cycle, as those introduce silicon complexity".
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1. kllrnohj ◴[27 Aug 24 20:37 UTC] No.41372708[source]▶
But that's not even close to true, either, eg any division or memory operation.

In practice there's no such thing as "RISC" or "CISC" anymore really, they've all pretty much converged. At best you can say "RISC" now just means that there aren't any mixed load + alu instructions, but those aren't really used in x86 much, either

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2. imtringued ◴[28 Aug 24 10:55 UTC] No.41378160[source]▶
You've hit the nail on the head. Really, when people complain about CISC vs RISC, they are mostly complaining about two particular things. The first is that x86 processors carry legacy baggage (aka they have had a long history of success that continues to this day) and the second is that x86 has a lot of variable length instructions. After that, most of the complaints are very nit-picky, such as the number of general purpose registers and how they are named.