←back to thread

Box64 and RISC-V in 2024: What It Takes to Run the Witcher 3 on RISC-V

(box86.org)
366 points pabs3 | 3 comments | 27 Aug 24 04:23 UTC | HN request time: 0.001s | source
Show context
Manfred ◴[27 Aug 24 08:31 UTC] No.41365540[source]▶
> At least in the context of x86 emulation, among all 3 architectures we support, RISC-V is the least expressive one.

RISC was explained to me as a reduced instruction set computer in computer science history classes, but I see a lot of articles and proposed new RISC-V profiles about "we just need a few more instructions to get feature parity".

I understand that RISC-V is just a convenient alternative to other platforms for most people, but does this also mean the RISC dream is dead?

replies(7): >>41365583 #>>41365644 #>>41365687 #>>41365974 #>>41366364 #>>41370373 #>>41370588 #
gary_0 ◴[27 Aug 24 09:09 UTC] No.41365687[source]▶
As I've heard it explained, RISC in practise is less about "an absolutely minimalist instruction set" and more about "don't add any assembly programmer conveniences or other such cleverness, rely on compilers instead of frontend silicon when possible".

Although as I recall from reading the RISC-V spec, RISC-V was rather particular about not adding "combo" instructions when common instruction sequences can be fused by the frontend.

My (far from expert) impression of RISC-V's shortcomings versus x86/ARM is more that the specs were written starting with the very basic embedded-chip stuff, and then over time more application-cpu extensions were added. (The base RV32I spec doesn't even include integer multiplication.) Unfortunately they took a long time to get around to finishing the bikeshedding on bit-twiddling and simd/vector extensions, which resulted in the current functionality gaps we're talking about.

So I don't think those gaps are due to RISC fundamentalism; there's no such thing.

replies(2): >>41365919 #>>41369318 #
Suppafly ◴[27 Aug 24 16:25 UTC] No.41369318[source]▶
>and more about "don't add any assembly programmer conveniences or other such cleverness, rely on compilers instead of frontend silicon when possible"

What are the advantages of that?

replies(3): >>41369498 #>>41369725 #>>41370346 #
1. adgjlsfhk1 ◴[27 Aug 24 16:51 UTC] No.41369725[source]▶
complexity that the compiler removes doesn't have to be handled by the CPU at runtime
replies(1): >>41371035 #
2. Suppafly ◴[27 Aug 24 18:28 UTC] No.41371035[source]▶
Sure but that's not necessarily at odds with "programmer conveniences or other such cleverness" is it?
replies(1): >>41375212 #
3. adgjlsfhk1 ◴[28 Aug 24 01:49 UTC] No.41375212[source]▶
it is in the sense that those are programmer conveniences only for assembly programmers and Riscv's view is that to the extent possible the assembly programmer interface should largely be handled by psuedo-instructions that disappear when your go to machine code rather than making the chip deal with them