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Box64 and RISC-V in 2024: What It Takes to Run the Witcher 3 on RISC-V

(box86.org)
366 points pabs3 | 4 comments | 27 Aug 24 04:23 UTC | HN request time: 0.902s | source
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nolist_policy ◴[27 Aug 24 11:28 UTC] No.41366371[source]▶
> The x86 instruction set is very very big. According to rough statistics, the ARM64 backend implements more than 1,600 x86 instructions in total, while the RV64 backend implements about 1,000 instructions

This is just insane and gets us full-circle to why we want RISC-V.

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1. patmorgan23 ◴[27 Aug 24 12:00 UTC] No.41366607[source]▶
Not really. RISC-V's benefits are not the "Reduced Instruction Set" part, it's the open ISA part. A small instruction set as actually has several disadvantages. It means you binary bigger because what was a single operation in x86 is now several in RISC-V, meaning more memory bandwidth and cache is taken up by instructions instead of data.

Modern CPUs are actually really good at deciding operations into micro-ops. And the flexibility of being able to implement a complex operation in microcode, or silicon is essential for CPU designers.

Is there a bunch of legacy crap in x86? Yeah. Does getting rid of dramatically increase the performance ceiling? Probably not.

The real benefit of RISC-V is anybody can use it. It's democratizing the ISA. No one has to pay a license to use it, they can just build their CPU design and go.

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2. zozbot234 ◴[27 Aug 24 12:18 UTC] No.41366716[source]▶
> Modern CPUs are actually really good at deciding operations into micro-ops.

The largest out-of-order CPUs are actually quite reliant on having high-performance decode that can be performed in parallel using multiple hardware units. Starting from a simplified instruction set with less legacy baggage can be an advantage in this context. RISC-V is also pretty unique among 64-bit RISC ISA's wrt. including compressed instructions support, which gives it code density comparable to x86 at a vastly improved simplicity of decode (For example, it only needs to read a few bits to determine which insns are 16-bit vs. 32-bit length).

3. panick21_ ◴[27 Aug 24 13:20 UTC] No.41367237[source]▶
> means you binary bigger .... meaning more memory bandwidth and cache

Except this isn't actually true.

> Does getting rid of dramatically increase the performance ceiling? Probably not.

No but it dramatically DECREASES the amount of investment necessary to reach that ceiling.

Assume you have 2 teams, each get the same amount of money. Then ask them to make the highest performing spec compatible chip. What team is gone win 99% of the time?

> And the flexibility of being able to implement a complex operation in microcode, or silicon is essential for CPU designers.

You can add microcode to a RISC-V chip if you want, most people just don't want to.

> The real benefit of RISC-V is anybody can use it.

That is true, but its also just a much better instruction set then x86 -_-

4. snvzz ◴[27 Aug 24 23:44 UTC] No.41374502[source]▶
>It means you binary bigger

False premise, as size tool shows RVA20(RV64GC) binaries were already smallest among 64bit architectures.

Code gets smaller still (rather than larger) with newer extensions such as B in RVA22.

As of recently, the same is true in 32bit when comparing rv32 against former best (thumb2). But it was quite close before to begin with.