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Box64 and RISC-V in 2024: What It Takes to Run the Witcher 3 on RISC-V

(box86.org)
366 points pabs3 | 8 comments | 27 Aug 24 04:23 UTC | HN request time: 0.336s | source | bottom
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Manfred ◴[27 Aug 24 08:31 UTC] No.41365540[source]▶
> At least in the context of x86 emulation, among all 3 architectures we support, RISC-V is the least expressive one.

RISC was explained to me as a reduced instruction set computer in computer science history classes, but I see a lot of articles and proposed new RISC-V profiles about "we just need a few more instructions to get feature parity".

I understand that RISC-V is just a convenient alternative to other platforms for most people, but does this also mean the RISC dream is dead?

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flanked-evergl ◴[27 Aug 24 08:41 UTC] No.41365583[source]▶
Is there a RISC dream? I think there is an efficiency "dream", there is a performance "dream", there is a cost "dream" — there are even low-complexity relative to cost, performance and efficiency "dreams" — but a RISC dream? Who cares more about RISC than cost, performance, efficiency and simplicity?
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1. impossiblefork ◴[27 Aug 24 08:56 UTC] No.41365643[source]▶
But we define the RISC dream as a dream that efficiency, performance and low-cost could be achieved by cores with very small instruction sets?
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2. flanked-evergl ◴[27 Aug 24 09:07 UTC] No.41365677[source]▶
If adding more instructions negatively impacts efficiency, performance, cost and complexity, nobody would do it.
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3. foldr ◴[27 Aug 24 09:11 UTC] No.41365691[source]▶
Probably true now, but in ye olde days, some instructions existed primarily to make assembly programming more convenient.

Assembly programming is a real pain in the RISCiest of RISC architectures, like SPARC. Here's an example from https://www.cs.clemson.edu/course/cpsc827/material/Code%20Ge...:

• All branches (including the one caused by CALL, below) take place after execution of the following instruction.

• The position immediately after a branch is the “delay slot” and the instruction found there is the “delay instruction”.

• If possible, place a useful instruction in the delay slot (one which can safely be done whether or not a conditional branch is taken).

• If not, place a NOP in the delay slot.

• Never place any other branch instruction in a delay slot.

• Do not use SET in a delay slot (only half of it is really there).

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4. fanf2 ◴[27 Aug 24 09:20 UTC] No.41365732[source]▶
Not small instruction sets, simplified instruction sets. RISC’s main trick is to reduce the number of addressing modes (eg, no memory indirect instructions) and reduce the number of memory operands per instruction to 0 or 1. Use the instruction encoding space for more registers instead.

The surviving CISCs, x86 and z390 are the least CISCy CISCs. The surviving RISCs, arm and power, are the least RISCy RISCs.

RISC V is a weird throwback in some aspects of its instruction set design.

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5. patmorgan23 ◴[27 Aug 24 12:05 UTC] No.41366636[source]▶
Only if decoder complexity/ efficiency is you bottleneck
6. panick21_ ◴[27 Aug 24 14:01 UTC] No.41367633[source]▶
Lets be real, its about business models. POWER was and is backed by IBM. ARM won on mobile. Does this mean POWER and ARM are better then MIPS, SPARC, PA-RISC, Am29000, i860? I don't think so.
7. pjc50 ◴[27 Aug 24 15:24 UTC] No.41368605{3}[source]▶
Delay slots were such a hack. ARM never needed them.
8. Symmetry ◴[28 Aug 24 11:21 UTC] No.41378302[source]▶
More details on how RISCy or CISCy various chips are:

https://userpages.umbc.edu/~vijay/mashey.on.risc.html

Notably x86 is one of the less CISCy CISCs so it looks like there might be a happy medium.