I got almost all of my wishes granted with RP2350

I think it's a good way to introduce these chips, and it's a great project, but the author's (frankly weird) beef with STM32H7 is detracting from the point they're trying to make:

> So, in conclusion, go replan all your STM32H7 projects with RP2350, save money, headaches, and time.

STM32H7 chips can run much faster and have a wider selection of peripherals than RP2350. RP2350 excels in some other dimensions, including the number of (heterogenous) cores. Either way, this is nowhere near apples-to-apples.

Further, they're not the only Cortex-M7 vendor, so if the conclusion is that STM32H7 sucks (it mostly doesn't), it doesn't follow that you should be instead using Cortex-M33 on RPi. You could be going with Microchip (hobbyist-friendly), NXP (preferred by many commercial buyers), or a number of lesser-known manufacturers.

1. Nobody has a wider selection of peripherals than a chip with 3 PIOs.

2. And my beef is personal - I spent months (MONTHS of my life) debugging the damn H7, only to find a set of huge bugs in the main reason I had been trying to use it (QSPI ram support), showed it to the manufacturer, and had them do nothing. Later they came back and, without admitting i was right about the bugs, said that "another customer is seeing same issues, what was the workaround you said found?" I told them that i'll share the workaround when they admit the problem. Silence since.

I fully reserve the right to be pissy at shitty companies in public on my website!

I'm not arguing you can't be angry with them, I'm just saying that to me, it detracts from the point about the new platform. Regarding #1, I'm sure you know that peripherals in the MCU world mean more than just digital I/O. Further, even in the digital domain, the reason PIO isn't more popular is that most people don't want to DIY complex communication protocols.

[edit: I retract this, I see you’ve had secretly in your possession to play with for over a year. You lucky dog. ]

> I have been anti-recommending STM’s chips to everyone for a few years now due to STM’s behaviour with regards to the clearly-demonstrated-to-them hardware issues.

You certainly reserve the right. However it is unclear to me why the recommendation to complaints over a months-long period is a product that has just been released.

Trying to ask in a very unbiased way since as a hobbyist I’m looking into ST, Microchip, and RP2040. For my part I’ve had two out of four RP2040 come to me dead on arrival, as part of two separate boards from different vendors - one being Pi Pico from Digilent. Not a ton of experience with Microchip but I hear they have their own problems. Nobody’s perfect, the question is how do the options compare.

> STM32H7 chips can run much faster

STM32H7 tops out at 600MHz. This has 2x 300MHz at 2-3 cycles/op FP64. So maybe your applications can fit into this?

ST is a zillion dollar company that should be hiring the talent capable of delivering product that match the features in their sales pamphlets. Integration is tricky but a company with STs deep pockets should be able to root cause or at least help troubleshoot an issue, not ask for a fix like some nepotism hire.

I don’t think the issue is QA related, ST released a chip that says it can perform X when the reality is it can not perform X.

they're complaining now because they still feel the pain now. while writing the article, they're thinking of how things would have been different on previous projects if they had had this chip, and that is digging up pain and they felt it should be expressed.

I don't know what's so unclear. Have you never had a strong opinion about someone else's stuff? Man, I have.

I'm seeing several statements of 2x300MHz, but the page [1] says 2x150MHz M33's..

I know the RP2040's overclock a lot but these are significantly more complex chips, it seems less likely they'll overclock to 2x the base frequency.

[1] https://www.raspberrypi.com/news/raspberry-pi-pico-2-our-new...

The STM32H7 and other M7 chips have caches - performance is night and day between 2x300MHz smaller, cacheless cores and chips with L1 caches (and things like TCM, etc.)

The SRAM in that H7 is running at commensurately-high speeds, as well.

Comparing an overclocked 2xM33 to a non-overclocked M7 is also probably a little inaccurate - that M7 will easily make more than the rated speed (not nearly as much as the RP2040 M0+, though.)

> 1. Nobody has a wider selection of peripherals than a chip with 3 PIOs.

NXP FlexIO says "Hello!"

It's 6 cycles for dadd/dsub, 16 for dmul, 51 for ddiv.

They should also be hiring people that can write clearly in their datasheets, but here we are, so...

As other posters have mentioned, this has 2 Cortex-M33 cores @ 150 MHz, not @ 300 MHz.

Cortex-M7 is in a different size class than Cortex-M33, it has a speed about 50% greater at the same clock frequency and it is also available at higher clock frequencies.

Cortex-M33 is the replacement for the older Cortex-M4 (while Cortex-M23 is the replacement for Cortex-M0+ and Cortex-M85 is the modern replacement for Cortex-M7).

While for a long time the Cortex-M MCUs had been available in 3 main sizes, Cortex-M0+, Cortex-M4 and Cortex-M7, for their modern replacements there is an additional size, Cortex-M55, which is intermediate between Cortex-M33 and Cortex-M85.

TFA states extensive 300Mhz OC with no special effort (and he's been evaluating pre-release versions for a year).

"It overclocks insanely well. I’ve been running the device at 300MHz in all of my projects with no issues at all."

Also

"Disclaimer: I was not paid or compensated for this article in any way. I was not asked to write it. I did not seek or obtain any approval from anyone to say anything I said. My early access to the RP2350 was not conditional on me saying something positive (or anything at all) about it publicly."

Thanks, I missed that.

FlexIO is (I think) powerful, however... I'm not sure if it's me or the way they describe it with all the bit-serialisers/shifters interacting - but I grok the PIO assembly a damn sight easier than FlexIO.

Maybe it's just me. Maybe.

> 6 cycles for dadd/dsub

I guess it depends whether you store to X (or Y), normalize & round (NRDD; is it really necessary after each addition?) and load X back every time.

Both X and Y have 64 bits of mantissa, 14 bits of exponent and 4 bits of flags, including sign. Some headroom compared to IEEE 754 fp64 53 mantissa and 11 bits of exponent, so I'd assume normalization might not be necessary after every step.

The addition (X = X + Y) itself presumably takes 2 cycles; running coprocessor instructions ADD0 and ADD1. 1 cycle more if normalization is always necessary. And for the simplest real world case, 1 cycle more for loading Y.

Regardless, there might be some room for hand optimizing tight fp64 loops.

Edit: This is based on my current understanding of the available documentation. I might very well be wrong.

I'm not an ST fanboy and they're not a vendor I use, but they are very popular in the 32-bit Cortex-M space, so they're clearly doing something right. Meanwhile, companies like Microchip that put effort into accessible documentation and tooling are getting table scraps.