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Optical PCIe 7.0 connection hits 128 GT/s

(www.tomshardware.com)
204 points WithinReason | 2 comments | 17 Jun 24 11:42 UTC | HN request time: 0.5s | source
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mistyvales ◴[18 Jun 24 00:21 UTC] No.40712753[source]▶
Here I am still on PCI-E 3.0...
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Arnavion ◴[18 Jun 24 00:24 UTC] No.40712764[source]▶
Most hardware (NVMe drives, GPUs, etc) doesn't run at more than 4.0 speeds anyway. The primary advantage of 5.0 and higher is that it'll allow that hardware to use fewer CPU lanes, eg what requires 4.0 x4 could use 6.0 x1.
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steelbrain ◴[18 Jun 24 05:16 UTC] No.40714274[source]▶
> eg what requires 4.0 x4 could use 6.0 x1

FWIW, this is only true for newer hardware. ie if you plugged in a pcie gen3x16 device into a pcie gen4x8 slot, although the bandwidth provided is in the same ballpark, the device will only run at pcie gen3x8.

So we'll need until the devices upgrade themselves to gen4 in this scenario to make use of higher bandwidth.

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Arnavion ◴[18 Jun 24 06:01 UTC] No.40714486[source]▶
I'm not saying the device itself would negotiate a higher PCIe version. I'm saying that the 4.0 x4 M.2 NVMe slot on your mobo would map to only one 6.0 CPU lane.
replies(1): >>40718279 #
seritools ◴[18 Jun 24 14:30 UTC] No.40718279[source]▶
Huh, I was pretty sure that you need an extra chip in-between. Otherwise, the 4 CPU lanes will just drop to 4.0 level.
replies(1): >>40719408 #
Arnavion ◴[18 Jun 24 16:06 UTC] No.40719408[source]▶
Yes you do.
replies(1): >>40720965 #
1. Dylan16807 ◴[18 Jun 24 19:00 UTC] No.40720965[source]▶
You'd need a bunch of those chips to make good use of a bunch of 6.0 lanes on the CPU, and at that point you're paying so much for the converters that I'm skeptical it would almost ever be worth it.

I expect consumer machines to keep doing some conversion and expansion in the chipset, but nowhere else. I expect servers to directly attach almost everything and drop down to smaller lane counts for large numbers of devices.

It's worth noting that when Kioxia first put out PCIe 5.0 EDSFF drives, they were marketing them as being optimized for 2 lanes at the higher speed.

replies(1): >>40721859 #
2. ◴[18 Jun 24 20:24 UTC] No.40721859[source]▶