TSMC looks to double down on U.S. chip factories as talks in Europe falter

I wonder how significant it is that there is all this worldwide expansion of chip making factories just as we get to 3nm architectures, I say that because there aren’t very many nm’s left, what happens when we get to zero?

It's mostly a marketing term right? They might do something like 0.5 or add some letters like X or whatever.

angstroms

We already ran out of microns in the 1990's.

NO! Bad unit!

I wonder if the end of chip performance improvements could cause a short term boost in manufacturing investment and sales. Instead of chip investments in products and data centers surely becoming obsolete in a few years, useable lifetimes could be measured in decades if the chip designs and performance are not expected to change. If you can get 30 years out of a data center investment instead of 5, you can spend a lot more money and amortized it for longer.

Silicon atoms are only 0.235nm apart. So at 1nm you only have 5 atoms left. At 0.2nm you have one atom lleft and it stops behaving like a semiconductor. So there are real physical limits to nm scale devices that don't apply to micron sized ones.

Admittedly were not as close to those limits as it seems since "nm" quoted on CPUs etc is no longer a literal size of the object. But we're getting there...

I think so. IBM recently produced a new "5nm" chip. In reality the physical size is closer to 24nm, if I remember correctly. The numbers you hear don't literally mean the physical size of the transistor, it refers to something else.

Ångström is the shit

Most chips are 2D. IBM made a 2nn equivalent in 2D, by using 3D.

lol

So we got 5 atoms left? Shit that’s not a lot is it.

I wonder what the abbreviation will be, it doesn’t have an obvious one.

>Admittedly were not as close to those limits as it seems since "nm" quoted on CPUs etc is no longer a literal size of the object. But we're getting there...

nm process numbers are based on the theoretical feature size that a planar transistor process would need to be equivalent to the used process. Since this number is purely theoretical the lower bound is zero, it can go well below the plank length.

It’s certainly interesting to think about. We’ve been accelerating these chip improvements at exponential rates for a lot of years, and essentially just as we hit the highest speed ever, and highest dependence, we are going to hit a brick wall of sorts. There’s going to be a massive spill over somewhere. Unless there’s some new fancy hardware invention, then the next thing to happen will be a software optimisation mania.