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A Superscalar Out-of-Order x86 Soft Processor for FPGA (2017)

(tspace.library.utoronto.ca)
90 points matt_d | 2 comments | 07 Mar 19 15:59 UTC | HN request time: 0s | source
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userbinator ◴[08 Mar 19 03:02 UTC] No.19334750[source]▶
Our microarchitecture achieves 2.7 times the per-clock performance of a performance-tuned Nios II/f, Alteraâ s fastest (RISC-like, single-issue, pipelined) soft processor, and 0.8 times the frequency, for a total performance improvement of 2.2 times.

It'd be very interesting to compare this to RISC-V.

replies(2): >>19334809 #>>19335267 #
1. pcwalton ◴[08 Mar 19 03:15 UTC] No.19334809[source]▶
Note that this the Nios II/f is an in-order CPU, while this is a superscalar CPU. A more relevant benchmark would be the superscalar dual-issue ARM Cortex-A9, illustrated in figure 13.4. It's about the same performance as that one if you average all the benchmarks.

In theory, RISC-V should be at about the same performance as ARMv8 (note that Cortex-A9 is ARMv7): https://news.ycombinator.com/item?id=15343287

replies(1): >>19335276 #
2. snvzz ◴[08 Mar 19 05:11 UTC] No.19335276[source]▶
>In theory, RISC-V should be at about the same performance as ARMv8

Or POWER9, the cpu with the fastest IPC. And it's RISC.

There's nothing to prevent RISC-V ISA from getting high performance implementations.