A Superscalar Out-of-Order x86 Soft Processor for FPGA (2017)

Section 1.1 makes a pretty good argument in favor.

What I am trying to say is that FPGA fabric is expensive, and at some point if you use too much, then it will push you to a new part. Most of the time I would guess it to be cheaper to have a separate processor for more intensive tasks. Of course if you have some IP that is partially implemented in a soft core, then it might not be practical to offload it to an external cpu.

Actually, I think FPGAs are amazingly cheap compared to what it would cost you to fab a chip of similar specs. A leading-edge FPGA will get you near-leading edge DSPs, memory blocks, SerDes, etc. What you _don't_ get is the frequency of a custom part for the full design (this is the FPGA overhead).

Simple RISC softcores run at 200-400 MHz in modern parts. Couple this with custom softcore accelerators and you can get very performant designs. The biggest issue with deploying FPGAs however is that it's much harder to design for, especially dealing with hard blocks, like memory controllers and PCIe.

Are there detailed writeups of people building these things into their systems? (Something like https://blog.cloudflare.com/building-fast-interpreters-in-ru... but for FPGAs instead of Rust).

>"Couple this with custom softcore accelerators and you can get very performant designs."

Can you elaborate on what these softcore accelerators are or how they work? Might you have any links?

This is not for commodity tasks, though. Think reimplementing an old x86 system on FPGA and using it to keep old software (games, utilities, cool demos) properly functioning, even for things that might not work properly with simple software emulation. With Intel now planning to abandon support for the BIOS and for 16-bit and 32-bit system boot in new x86 architectures, an independent reimplementation is something we should have.

I don't have good references handy where I am right now, but Hotchips a couple of years ago had many examples, including a Memcache accelerator.

A more down-to-earth example shipped with an Arrow FPGA dev kit I got: they took a software and ported MPG123 (mp3 decoding). They then profiled it and isolated a candidate for acceleration (some moderately wide integer operation). The result saved meaningful amount of CPU cycles and power. (The FPGA board was battery driven, which is still unusual).

Most decent sized designs, hard or soft, have little processors embedded in them in addition to their core logic. It's an interesting space/time/ease of development trade-off between a special little processor, and doing the same work in just logic.

GPUs are pretty well documented (relatively speaking), so they make a good case study. Generally special processors will handle FIFO pulling (so the part that reads the command lists), DMA engines, power management, video codecs, DRM key management, and some other miscellaneous pieces (like run this code on the GPU' on certain interrupts, instead of interrupting the CPU). And that's all in addition to the shader cores you normally think of as 'the GPU'.

In the past, I've used simple processor cores in FPGAs for motor control.