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A Superscalar Out-of-Order x86 Soft Processor for FPGA (2017)

(tspace.library.utoronto.ca)
90 points matt_d | 3 comments | 07 Mar 19 15:59 UTC | HN request time: 0s | source
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hak8or ◴[07 Mar 19 22:29 UTC] No.19333225[source]▶
How is this legally handled considering amd owns x86-64 and Intel owns x86?

As long as it's not used in commercial settings, will they pretend not to see it while users are in a legally gray area?

replies(1): >>19333272 #
1. wk_end ◴[07 Mar 19 22:33 UTC] No.19333272[source]▶
This is x86 only, and a quick skim of the dissertation suggests that it doesn't implement any post-P6 (Pentium Pro) instructions. The P6 is 24 years old now so presumably all patents are expired?
replies(1): >>19334759 #
2. userbinator ◴[08 Mar 19 03:04 UTC] No.19334759[source]▶
The last time I looked, the MMX patents were close to expiry too, and by now they might be.
replies(1): >>19335466 #
3. Const-me ◴[08 Mar 19 05:59 UTC] No.19335466[source]▶
MMX is from P5.

P6 supports MMX and later revisions SSE 1.

The next one after P6 is NetBurst, it introduced SSE2 and later revisions SSE3.