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Intel x86 considered harmful – survey of attacks against x86 over last 10 years

(blog.invisiblethings.org)
276 points chei0aiV | 4 comments | 27 Oct 15 14:51 UTC | HN request time: 0s | source
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hmage ◴[27 Oct 15 15:26 UTC] No.10458577[source]▶
Yes yes, everyone should move to MCST Elbrus :D
replies(1): >>10461158 #
nickpsecurity ◴[27 Oct 15 21:10 UTC] No.10461158[source]▶
No, use Gaisler's stuff:

http://www.gaisler.com/index.php/products/ipcores/soclibrary

Also SPARC but with plenty GPL. Has a quad-core, too, with all of them designed to be easily modified and re-synthesized. :)

replies(1): >>10462441 #
e12e ◴[28 Oct 15 01:54 UTC] No.10462441[source]▶
There are a few of these (open architectures) - but does anyone know how much (ballpark) it'd cost to make something like the Raspberry Pi 2 (ie: a full SoC, with gig ethernet, usb, hdmi, sata) support? Say 10.000 units?

I'm assuming it'd be expensive, as it doesn't appear anyone's doing it...

replies(2): >>10462904 #>>10468534 #
alexforencich ◴[28 Oct 15 04:54 UTC] No.10462904[source]▶
Several million dollars. Everything is extremely expensive - IP licenses, ASIC layout software licenses, simulation and verification software and possibly hardware, mask costs, line setup costs, wafer production costs, packaging costs, testing costs, etc.
replies(2): >>10463014 #>>10468540 #
e12e ◴[28 Oct 15 05:45 UTC] No.10463014[source]▶
Ip licences for gpled cpu cores and schemas? Several million doesn't sound that bad. Means that the bar moves to 100k rather than 10k units (if the goal is to break even in the short term). And it's tricky to sell 20k units/year for five years, as the cost to upgrade (clock, ram) would probably be in the same ballbark aa initial investment.?
replies(1): >>10467537 #
alexforencich ◴[28 Oct 15 21:23 UTC] No.10467537[source]▶
IP licenses for things like analog clock management components/PLLs, analog Ethernet PHYs, analog serializers and deserializers for HDMI, SATA, USB 3, etc. These are all mixed-signal components. I am not aware of any open source designs for any of these for modern ASIC targets. Most open source designs target FPGAs which already have these components built onto the FPGA itself (i.e. the open source design uses the module as a 'black box'). These will probably come in GDSII form (actual layout, not a schematic, RTL, etc.) for a specific process with a specific foundry. If you want to design those yourself, then you would have to get additional licenses for analog design and simulation suites. And you might have to re-spin a couple of times (with millions of $ in mask costs) on each targeted process technology to get the kinks worked out.
replies(1): >>10468566 #
1. e12e ◴[29 Oct 15 01:04 UTC] No.10468566[source]▶
Thank you for clarifying. Basically I thought maybe something like:

http://opencores.org/donation

already existed - but apparently not (except for targeting FPGAs as you mention) ?

replies(1): >>10468638 #
2. nickpsecurity ◴[29 Oct 15 01:27 UTC] No.10468638[source]▶
He addressed your point when he said most of them target FPGA's and often leverage what's already on them. I'll add that the quality, documentation, and so on at opencores.org seems questionable given all the complaints I read from pro's and amateurs alike. Some are good but I'm not qualified to say past what was ASIC-proven.

The analog stuff he mentioned is really tricky on any advanced node. Everything is difficult at least. It all needs good tooling that's had around a billion a year in R&D (Big Three) going back over a decade to get to the point they are. OSS tooling is getting better, esp for FPGA's. However, open-source ASIC's are going to happen with open source development model. Like many great things, they'll be built by teams of pro's and then open-sourceD. Gotta motivate them to do that. Hence, my development models in the other post.

replies(1): >>10468790 #
3. e12e ◴[29 Oct 15 02:11 UTC] No.10468790[source]▶
Right. Which is of course why we have stuff like the NASA/ESA making and releasing designs - big government projects with highly skilled staff. But they don't have much interest in releasing a "personal computer" or a "smart phone" (I'm sure they'd love to have an open hw platform to use for smart phones and tablets - or work stations and super computers, just that it's not high up on the list of priorities in the "millions of dollars" budget lists).

[ed: I'm thinking of things like LEON etc - but as mentioned, and as I understand it, for the ASIC case, maybe not the whole eval board is open. And it's not really in the same ballpark as the dual/quad multi-GHz cpus we've come to expect from low-end hard-ware:

http://www.gaisler.com/index.php/products/boards/gr-cpci-leo... ]

replies(1): >>10468965 #
4. nickpsecurity ◴[29 Oct 15 03:01 UTC] No.10468965{3}[source]▶
Oh, let me be clear that any starting point will definitely have more work to do and will never be in ballpark as top Intel/AMD/IBM CPU's. The reason is that they use large teams of pro's with the best tools often doing full-custom HW development. Full-custom means they'll do plenty to improve HDL, RTL, and even wiring of gates they use. Think of Standard Cell as Java web applications with full custom being like delivering a whole platform with a board, firmware, assembler, OS components, and native applications. That's maybe illustrative of the differences in skills and complexity.

Example of custom design flow http://viplab.cs.nctu.edu.tw/course/VLSI_SOC2009_Fall/VLSI_L...

Note: Load up this right next to the simple, 90nm MCU PDF I gave you and compare the two. I think that you'll easily see the difference in complexity. One you'll be able to mostly follow just googling terms and understand a lot of what they're doing. You're not going to understand the specifics of the full-custom flow at all. Simply too much domain knowledge built into it that combines years of analog and digital design knowledge. Top CPU's hit their benchmarks using full-custom for pipelines, caches, etc.

Example of verification that goes into making those monstrosities work:

http://fvclasspsu2009q1.pbworks.com/f/Yang-GSTEIntroPSU2009....

So, yeah, getting to that level of performance would be really hard work. The good news is that modern processors, esp x86, are lots of baggage that drains performance that we don't need. Simpler cores in large numbers with accelerators can be much easier to design and perform much better. Like so:

http://www.cavium.com/OCTEON-III_CN7XXX.html

Now, that's 28nm for sure. Point remains, though, as Cavium didn't have nearly the financial resources of Intel despite their processors smoking them in a shorter amount of time. Adapteva's 64-core Epiphany accelerator was likewise created with a few million dollars by pro's and careful choice of tooling. So, better architecture can make up for the lack of speed that comes from full-custom.