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276 points chei0aiV | 6 comments | | HN request time: 0.837s | source | bottom
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pjc50 ◴[] No.10458874[source]
"System management mode" is a tremendous wart and should be removed wholesale, with Intel adopting a more ARM-style trusted boot chain with explicit cooperation from the OS or hypervisor. And while you're at it, kill UEFI and install a pony for me.

(Seriously, SMM serves either bizarre ILO features that high-end vendors like but are rarely used, or security agencies looking for a layer to hide in.)

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1. pgeorgi ◴[] No.10459094[source]
SMM is used all the time:

Several Intel chipset generations require certain register writes on shutdown (disable busmaster) or they won't _actually_ shut down. Operating systems aren't aware of that. (https://github.com/coreboot/coreboot/blob/master/src/southbr...)

UEFI Secure Boot requires "authenticated variables", which can be updated by the OS (after checking authentication, using a signature scheme). UEFI code resides somewhere in memory, so the OS (or ring0 code) could opt to bypass the verification and simply rewrite those variables. The recommended (but not required) solution is to move variable update to SMM. (https://firmware.intel.com/sites/default/files/resources/A_T...)

Several hardware features are actually implemented in SMM. I've seen SMM-based handling of certain special keys (eg. "disable Wifi" button) where ACPI grabs the event, then traps into SMM using a magic IO port.

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2. pdkl95 ◴[] No.10459277[source]
> and simply rewrite those variables

Good luck trying that once that memory is encrypted with SGX.

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3. pgeorgi ◴[] No.10459350[source]
SGX is too complex for such purposes, and it also doesn't provide access levels to hardware.

The alternative to hooking into UEFI code would be to just write to flash by yourself. SMM has additional permissions there.

4. Nelson69 ◴[] No.10461503[source]
Yeah, I was going to say, I've seen hardware were advertised features were implemented with SMM. You could possibly take it away but it sure does enable a lot of nice hardware fixes without re-spinning silicon.

Some implementations it'll really screw up any RT plans you might have...

5. caf ◴[] No.10462094[source]
Couldn't those register writes required on shutdown be included in ACPI?
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6. pgeorgi ◴[] No.10463442[source]
Since it's traversing the PCI bus hierarchy, not easily.

There are also a number of shortcuts for "shutdown is just two writes to a given register" that some OS probably expect to be around these days (a field in FADT) that I'm not sure how a complex ACPI shutdown routine would fare in practice.